SAM3U UDPHS
USB High Speed Device Port (UDPHS) User Interface
Registers
Address | Register | Name | Access | Reset |
---|---|---|---|---|
0x400A4000 | UDPHS Control Register | UDPHS_CTRL | read-write | 0x00000200 |
0x400A4004 | UDPHS Frame Number Register | UDPHS_FNUM | read-only | 0x00000000 |
0x400A4010 | UDPHS Interrupt Enable Register | UDPHS_IEN | read-write | 0x00000010 |
0x400A4014 | UDPHS Interrupt Status Register | UDPHS_INTSTA | read-only | 0x00000000 |
0x400A4018 | UDPHS Clear Interrupt Register | UDPHS_CLRINT | write-only | - |
0x400A401C | UDPHS Endpoints Reset Register | UDPHS_EPTRST | write-only | - |
0x400A40E0 | UDPHS Test Register | UDPHS_TST | read-write | 0x00000000 |
0x400A40F0 | UDPHS Name1 Register | UDPHS_IPNAME1 | read-only | 0x48555342 |
0x400A40F4 | UDPHS Name2 Register | UDPHS_IPNAME2 | read-only | 0x32444556 |
0x400A40F8 | UDPHS Features Register | UDPHS_IPFEATURES | read-only | - |
0x400A4100 | UDPHS Endpoint Configuration Register (endpoint = 0) | UDPHS_EPTCFG0 | read-write | 0x00000000 |
0x400A4104 | UDPHS Endpoint Control Enable Register (endpoint = 0) | UDPHS_EPTCTLENB0 | write-only | - |
0x400A4108 | UDPHS Endpoint Control Disable Register (endpoint = 0) | UDPHS_EPTCTLDIS0 | write-only | - |
0x400A410C | UDPHS Endpoint Control Register (endpoint = 0) | UDPHS_EPTCTL0 | read-only | 0x00000000 |
0x400A4114 | UDPHS Endpoint Set Status Register (endpoint = 0) | UDPHS_EPTSETSTA0 | write-only | - |
0x400A4118 | UDPHS Endpoint Clear Status Register (endpoint = 0) | UDPHS_EPTCLRSTA0 | write-only | - |
0x400A411C | UDPHS Endpoint Status Register (endpoint = 0) | UDPHS_EPTSTA0 | read-only | 0x00000040 |
0x400A4120 | UDPHS Endpoint Configuration Register (endpoint = 1) | UDPHS_EPTCFG1 | read-write | 0x00000000 |
0x400A4124 | UDPHS Endpoint Control Enable Register (endpoint = 1) | UDPHS_EPTCTLENB1 | write-only | - |
0x400A4128 | UDPHS Endpoint Control Disable Register (endpoint = 1) | UDPHS_EPTCTLDIS1 | write-only | - |
0x400A412C | UDPHS Endpoint Control Register (endpoint = 1) | UDPHS_EPTCTL1 | read-only | 0x00000000 |
0x400A4134 | UDPHS Endpoint Set Status Register (endpoint = 1) | UDPHS_EPTSETSTA1 | write-only | - |
0x400A4138 | UDPHS Endpoint Clear Status Register (endpoint = 1) | UDPHS_EPTCLRSTA1 | write-only | - |
0x400A413C | UDPHS Endpoint Status Register (endpoint = 1) | UDPHS_EPTSTA1 | read-only | 0x00000040 |
0x400A4140 | UDPHS Endpoint Configuration Register (endpoint = 2) | UDPHS_EPTCFG2 | read-write | 0x00000000 |
0x400A4144 | UDPHS Endpoint Control Enable Register (endpoint = 2) | UDPHS_EPTCTLENB2 | write-only | - |
0x400A4148 | UDPHS Endpoint Control Disable Register (endpoint = 2) | UDPHS_EPTCTLDIS2 | write-only | - |
0x400A414C | UDPHS Endpoint Control Register (endpoint = 2) | UDPHS_EPTCTL2 | read-only | 0x00000000 |
0x400A4154 | UDPHS Endpoint Set Status Register (endpoint = 2) | UDPHS_EPTSETSTA2 | write-only | - |
0x400A4158 | UDPHS Endpoint Clear Status Register (endpoint = 2) | UDPHS_EPTCLRSTA2 | write-only | - |
0x400A415C | UDPHS Endpoint Status Register (endpoint = 2) | UDPHS_EPTSTA2 | read-only | 0x00000040 |
0x400A4160 | UDPHS Endpoint Configuration Register (endpoint = 3) | UDPHS_EPTCFG3 | read-write | 0x00000000 |
0x400A4164 | UDPHS Endpoint Control Enable Register (endpoint = 3) | UDPHS_EPTCTLENB3 | write-only | - |
0x400A4168 | UDPHS Endpoint Control Disable Register (endpoint = 3) | UDPHS_EPTCTLDIS3 | write-only | - |
0x400A416C | UDPHS Endpoint Control Register (endpoint = 3) | UDPHS_EPTCTL3 | read-only | 0x00000000 |
0x400A4174 | UDPHS Endpoint Set Status Register (endpoint = 3) | UDPHS_EPTSETSTA3 | write-only | - |
0x400A4178 | UDPHS Endpoint Clear Status Register (endpoint = 3) | UDPHS_EPTCLRSTA3 | write-only | - |
0x400A417C | UDPHS Endpoint Status Register (endpoint = 3) | UDPHS_EPTSTA3 | read-only | 0x00000040 |
0x400A4180 | UDPHS Endpoint Configuration Register (endpoint = 4) | UDPHS_EPTCFG4 | read-write | 0x00000000 |
0x400A4184 | UDPHS Endpoint Control Enable Register (endpoint = 4) | UDPHS_EPTCTLENB4 | write-only | - |
0x400A4188 | UDPHS Endpoint Control Disable Register (endpoint = 4) | UDPHS_EPTCTLDIS4 | write-only | - |
0x400A418C | UDPHS Endpoint Control Register (endpoint = 4) | UDPHS_EPTCTL4 | read-only | 0x00000000 |
0x400A4194 | UDPHS Endpoint Set Status Register (endpoint = 4) | UDPHS_EPTSETSTA4 | write-only | - |
0x400A4198 | UDPHS Endpoint Clear Status Register (endpoint = 4) | UDPHS_EPTCLRSTA4 | write-only | - |
0x400A419C | UDPHS Endpoint Status Register (endpoint = 4) | UDPHS_EPTSTA4 | read-only | 0x00000040 |
0x400A41A0 | UDPHS Endpoint Configuration Register (endpoint = 5) | UDPHS_EPTCFG5 | read-write | 0x00000000 |
0x400A41A4 | UDPHS Endpoint Control Enable Register (endpoint = 5) | UDPHS_EPTCTLENB5 | write-only | - |
0x400A41A8 | UDPHS Endpoint Control Disable Register (endpoint = 5) | UDPHS_EPTCTLDIS5 | write-only | - |
0x400A41AC | UDPHS Endpoint Control Register (endpoint = 5) | UDPHS_EPTCTL5 | read-only | 0x00000000 |
0x400A41B4 | UDPHS Endpoint Set Status Register (endpoint = 5) | UDPHS_EPTSETSTA5 | write-only | - |
0x400A41B8 | UDPHS Endpoint Clear Status Register (endpoint = 5) | UDPHS_EPTCLRSTA5 | write-only | - |
0x400A41BC | UDPHS Endpoint Status Register (endpoint = 5) | UDPHS_EPTSTA5 | read-only | 0x00000040 |
0x400A41C0 | UDPHS Endpoint Configuration Register (endpoint = 6) | UDPHS_EPTCFG6 | read-write | 0x00000000 |
0x400A41C4 | UDPHS Endpoint Control Enable Register (endpoint = 6) | UDPHS_EPTCTLENB6 | write-only | - |
0x400A41C8 | UDPHS Endpoint Control Disable Register (endpoint = 6) | UDPHS_EPTCTLDIS6 | write-only | - |
0x400A41CC | UDPHS Endpoint Control Register (endpoint = 6) | UDPHS_EPTCTL6 | read-only | 0x00000000 |
0x400A41D4 | UDPHS Endpoint Set Status Register (endpoint = 6) | UDPHS_EPTSETSTA6 | write-only | - |
0x400A41D8 | UDPHS Endpoint Clear Status Register (endpoint = 6) | UDPHS_EPTCLRSTA6 | write-only | - |
0x400A41DC | UDPHS Endpoint Status Register (endpoint = 6) | UDPHS_EPTSTA6 | read-only | 0x00000040 |
0x400A4300 | UDPHS DMA Next Descriptor Address Register (channel = 0) | UDPHS_DMANXTDSC0 | read-write | 0x00000000 |
0x400A4304 | UDPHS DMA Channel Address Register (channel = 0) | UDPHS_DMAADDRESS0 | read-write | 0x00000000 |
0x400A4308 | UDPHS DMA Channel Control Register (channel = 0) | UDPHS_DMACONTROL0 | read-write | 0x00000000 |
0x400A430C | UDPHS DMA Channel Status Register (channel = 0) | UDPHS_DMASTATUS0 | read-write | 0x00000000 |
0x400A4310 | UDPHS DMA Next Descriptor Address Register (channel = 1) | UDPHS_DMANXTDSC1 | read-write | 0x00000000 |
0x400A4314 | UDPHS DMA Channel Address Register (channel = 1) | UDPHS_DMAADDRESS1 | read-write | 0x00000000 |
0x400A4318 | UDPHS DMA Channel Control Register (channel = 1) | UDPHS_DMACONTROL1 | read-write | 0x00000000 |
0x400A431C | UDPHS DMA Channel Status Register (channel = 1) | UDPHS_DMASTATUS1 | read-write | 0x00000000 |
0x400A4320 | UDPHS DMA Next Descriptor Address Register (channel = 2) | UDPHS_DMANXTDSC2 | read-write | 0x00000000 |
0x400A4324 | UDPHS DMA Channel Address Register (channel = 2) | UDPHS_DMAADDRESS2 | read-write | 0x00000000 |
0x400A4328 | UDPHS DMA Channel Control Register (channel = 2) | UDPHS_DMACONTROL2 | read-write | 0x00000000 |
0x400A432C | UDPHS DMA Channel Status Register (channel = 2) | UDPHS_DMASTATUS2 | read-write | 0x00000000 |
0x400A4330 | UDPHS DMA Next Descriptor Address Register (channel = 3) | UDPHS_DMANXTDSC3 | read-write | 0x00000000 |
0x400A4334 | UDPHS DMA Channel Address Register (channel = 3) | UDPHS_DMAADDRESS3 | read-write | 0x00000000 |
0x400A4338 | UDPHS DMA Channel Control Register (channel = 3) | UDPHS_DMACONTROL3 | read-write | 0x00000000 |
0x400A433C | UDPHS DMA Channel Status Register (channel = 3) | UDPHS_DMASTATUS3 | read-write | 0x00000000 |
0x400A4340 | UDPHS DMA Next Descriptor Address Register (channel = 4) | UDPHS_DMANXTDSC4 | read-write | 0x00000000 |
0x400A4344 | UDPHS DMA Channel Address Register (channel = 4) | UDPHS_DMAADDRESS4 | read-write | 0x00000000 |
0x400A4348 | UDPHS DMA Channel Control Register (channel = 4) | UDPHS_DMACONTROL4 | read-write | 0x00000000 |
0x400A434C | UDPHS DMA Channel Status Register (channel = 4) | UDPHS_DMASTATUS4 | read-write | 0x00000000 |
0x400A4350 | UDPHS DMA Next Descriptor Address Register (channel = 5) | UDPHS_DMANXTDSC5 | read-write | 0x00000000 |
0x400A4354 | UDPHS DMA Channel Address Register (channel = 5) | UDPHS_DMAADDRESS5 | read-write | 0x00000000 |
0x400A4358 | UDPHS DMA Channel Control Register (channel = 5) | UDPHS_DMACONTROL5 | read-write | 0x00000000 |
0x400A435C | UDPHS DMA Channel Status Register (channel = 5) | UDPHS_DMASTATUS5 | read-write | 0x00000000 |
Register Fields
UDPHS UDPHS Control Register
Name: UDPHS_CTRL
Access: read-write
Address: 0x400A4000
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | PULLD_DIS | REWAKEUP | DETACH | EN_UDPHS |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FADDR_EN | DEV_ADDR |
- DEV_ADDR: UDPHS Address
- FADDR_EN: Function Address Enable
Value Name Description 0 - Device is not in address state (read), or only the default function address is used (write). 1 - Device is in address state (read), or this bit is set by the device firmware after a successful status phase of a SET_ADDRESS transaction (write). When set, the only address accepted by the UDPHS controller is the one stored in the UDPHS Address field. It will not be cleared afterwards by the device firmware. It is cleared by hardware on hardware reset, or when UDPHS bus reset is received. - EN_UDPHS: UDPHS Enable
Value Name Description 0 - UDPHS is disabled (read), or this bit disables and resets the UDPHS controller (write). Disable the UTMI transceiver. The UTMI may disable the pull-up. 1 - UDPHS is enabled (read), or this bit enables the UDPHS controller (write). - DETACH: Detach Command
Value Name Description 0 - UDPHS is attached (read), or this bit pulls up the DP line (attach command) (write). 1 - UDPHS is detached, UTMI transceiver is suspended (read), or this bit simulates a detach on the UDPHS line and forces the UTMI transceiver into suspend state (Suspend M = 0) (write). - REWAKEUP: Send Remote Wake Up
Value Name Description 0 - Remote Wake Up is disabled (read), or this bit has no effect (write). 1 - Remote Wake Up is enabled (read), or this bit forces an external interrupt on the UDPHS controller for Remote Wake UP purposes. - PULLD_DIS: Pull-Down Disable
-
-
UDPHS UDPHS Frame Number Register
Name: UDPHS_FNUM
Access: read-only
Address: 0x400A4004
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
FNUM_ERR | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | FRAME_NUMBER | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FRAME_NUMBER | MICRO_FRAME_NUM |
- MICRO_FRAME_NUM: Microframe Number
- FRAME_NUMBER: Frame Number as defined in the Packet Field Formats
- FNUM_ERR: Frame Number CRC Error
-
-
-
UDPHS UDPHS Interrupt Enable Register
Name: UDPHS_IEN
Access: read-write
Address: 0x400A4010
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | EPT_6 | EPT_5 | EPT_4 | EPT_3 | EPT_2 | EPT_1 | EPT_0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UPSTR_RES | ENDOFRSM | WAKE_UP | ENDRESET | INT_SOF | MICRO_SOF | DET_SUSPD | - |
- DET_SUSPD: Suspend Interrupt Enable
Value Name Description 0 - disable Suspend Interrupt. 1 - enable Suspend Interrupt. - MICRO_SOF: Micro-SOF Interrupt Enable
Value Name Description 0 - disable Micro-SOF Interrupt. 1 - enable Micro-SOF Interrupt. - INT_SOF: SOF Interrupt Enable
Value Name Description 0 - disable SOF Interrupt. 1 - enable SOF Interrupt. - ENDRESET: End Of Reset Interrupt Enable
Value Name Description 0 - disable End Of Reset Interrupt. 1 - enable End Of Reset Interrupt. Automatically enabled after USB reset. - WAKE_UP: Wake Up CPU Interrupt Enable
Value Name Description 0 - disable Wake Up CPU Interrupt. 1 - enable Wake Up CPU Interrupt. - ENDOFRSM: End Of Resume Interrupt Enable
Value Name Description 0 - disable Resume Interrupt. 1 - enable Resume Interrupt. - UPSTR_RES: Upstream Resume Interrupt Enable
Value Name Description 0 - disable Upstream Resume Interrupt. 1 - enable Upstream Resume Interrupt. - EPT_0: Endpoint 0 Interrupt Enable
Value Name Description 0 - disable the interrupts for this endpoint. 1 - enable the interrupts for this endpoint. - EPT_1: Endpoint 1 Interrupt Enable
Value Name Description 0 - disable the interrupts for this endpoint. 1 - enable the interrupts for this endpoint. - EPT_2: Endpoint 2 Interrupt Enable
Value Name Description 0 - disable the interrupts for this endpoint. 1 - enable the interrupts for this endpoint. - EPT_3: Endpoint 3 Interrupt Enable
Value Name Description 0 - disable the interrupts for this endpoint. 1 - enable the interrupts for this endpoint. - EPT_4: Endpoint 4 Interrupt Enable
Value Name Description 0 - disable the interrupts for this endpoint. 1 - enable the interrupts for this endpoint. - EPT_5: Endpoint 5 Interrupt Enable
Value Name Description 0 - disable the interrupts for this endpoint. 1 - enable the interrupts for this endpoint. - EPT_6: Endpoint 6 Interrupt Enable
Value Name Description 0 - disable the interrupts for this endpoint. 1 - enable the interrupts for this endpoint. - DMA_1: DMA Channel 1 Interrupt Enable
Value Name Description 0 - disable the interrupts for this channel. 1 - enable the interrupts for this channel. - DMA_2: DMA Channel 2 Interrupt Enable
Value Name Description 0 - disable the interrupts for this channel. 1 - enable the interrupts for this channel. - DMA_3: DMA Channel 3 Interrupt Enable
Value Name Description 0 - disable the interrupts for this channel. 1 - enable the interrupts for this channel. - DMA_4: DMA Channel 4 Interrupt Enable
Value Name Description 0 - disable the interrupts for this channel. 1 - enable the interrupts for this channel. - DMA_5: DMA Channel 5 Interrupt Enable
Value Name Description 0 - disable the interrupts for this channel. 1 - enable the interrupts for this channel. - DMA_6: DMA Channel 6 Interrupt Enable
Value Name Description 0 - disable the interrupts for this channel. 1 - enable the interrupts for this channel.
UDPHS UDPHS Interrupt Status Register
Name: UDPHS_INTSTA
Access: read-only
Address: 0x400A4014
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | EPT_6 | EPT_5 | EPT_4 | EPT_3 | EPT_2 | EPT_1 | EPT_0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UPSTR_RES | ENDOFRSM | WAKE_UP | ENDRESET | INT_SOF | MICRO_SOF | DET_SUSPD | SPEED |
- SPEED: Speed Status
Value Name Description 0 - reset by hardware when the hardware is in Full Speed mode. 1 - set by hardware when the hardware is in High Speed mode - DET_SUSPD: Suspend Interrupt
Value Name Description 0 - cleared by setting the DET_SUSPD bit in UDPHS_CLRINT register 1 - set by hardware when a UDPHS Suspend (Idle bus for three frame periods, a J state for 3 ms) is detected. This triggers a UDPHS interrupt when the DET_SUSPD bit is set in UDPHS_IEN register. - MICRO_SOF: Micro Start Of Frame Interrupt
Value Name Description 0 - cleared by setting the MICRO_SOF bit in UDPHS_CLRINT register. 1 - set by hardware when an UDPHS micro start of frame PID (SOF) has been detected (every 125 us) or synthesized by the macro. This triggers a UDPHS interrupt when the MICRO_SOF bit is set in UDPHS_IEN. In case of detected SOF, the MICRO_FRAME_NUM field in UDPHS_FNUM register is incremented and the FRAME_NUMBER field doesn't change. - INT_SOF: Start Of Frame Interrupt
Value Name Description 0 - cleared by setting the INT_SOF bit in UDPHS_CLRINT. 1 - set by hardware when an UDPHS Start Of Frame PID (SOF) has been detected (every 1 ms) or synthesized by the macro. This triggers a UDPHS interrupt when the INT_SOF bit is set in UDPHS_IEN register. In case of detected SOF, in High Speed mode, the MICRO_FRAME_NUMBER field is cleared in UDPHS_FNUM register and the FRAME_NUMBER field is updated. - ENDRESET: End Of Reset Interrupt
Value Name Description 0 - cleared by setting the ENDRESET bit in UDPHS_CLRINT. 1 - set by hardware when an End Of Reset has been detected by the UDPHS controller. This triggers a UDPHS interrupt when the ENDRESET bit is set in UDPHS_IEN. - WAKE_UP: Wake Up CPU Interrupt
Value Name Description 0 - cleared by setting the WAKE_UP bit in UDPHS_CLRINT. 1 - set by hardware when the UDPHS controller is in SUSPEND state and is re-activated by a filtered non-idle signal from the UDPHS line (not by an upstream resume). This triggers a UDPHS interrupt when the WAKE_UP bit is set in UDPHS_IEN register. When receiving this interrupt, the user has to enable the device controller clock prior to operation. - ENDOFRSM: End Of Resume Interrupt
Value Name Description 0 - cleared by setting the ENDOFRSM bit in UDPHS_CLRINT. 1 - set by hardware when the UDPHS controller detects a good end of resume signal initiated by the host. This triggers a UDPHS interrupt when the ENDOFRSM bit is set in UDPHS_IEN. - UPSTR_RES: Upstream Resume Interrupt
Value Name Description 0 - cleared by setting the UPSTR_RES bit in UDPHS_CLRINT. 1 - set by hardware when the UDPHS controller is sending a resume signal called "upstream resume". This triggers a UDPHS interrupt when the UPSTR_RES bit is set in UDPHS_IEN. - EPT_0: Endpoint 0 Interrupt
Value Name Description 0 - reset when the UDPHS_EPTSTAx interrupt source is cleared. 1 - set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN. - EPT_1: Endpoint 1 Interrupt
Value Name Description 0 - reset when the UDPHS_EPTSTAx interrupt source is cleared. 1 - set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN. - EPT_2: Endpoint 2 Interrupt
Value Name Description 0 - reset when the UDPHS_EPTSTAx interrupt source is cleared. 1 - set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN. - EPT_3: Endpoint 3 Interrupt
Value Name Description 0 - reset when the UDPHS_EPTSTAx interrupt source is cleared. 1 - set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN. - EPT_4: Endpoint 4 Interrupt
Value Name Description 0 - reset when the UDPHS_EPTSTAx interrupt source is cleared. 1 - set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN. - EPT_5: Endpoint 5 Interrupt
Value Name Description 0 - reset when the UDPHS_EPTSTAx interrupt source is cleared. 1 - set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN. - EPT_6: Endpoint 6 Interrupt
Value Name Description 0 - reset when the UDPHS_EPTSTAx interrupt source is cleared. 1 - set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN. - DMA_1: DMA Channel 1 Interrupt
Value Name Description 0 - reset when the UDPHS_DMASTATUSx interrupt source is cleared. 1 - set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN. - DMA_2: DMA Channel 2 Interrupt
Value Name Description 0 - reset when the UDPHS_DMASTATUSx interrupt source is cleared. 1 - set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN. - DMA_3: DMA Channel 3 Interrupt
Value Name Description 0 - reset when the UDPHS_DMASTATUSx interrupt source is cleared. 1 - set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN. - DMA_4: DMA Channel 4 Interrupt
Value Name Description 0 - reset when the UDPHS_DMASTATUSx interrupt source is cleared. 1 - set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN. - DMA_5: DMA Channel 5 Interrupt
Value Name Description 0 - reset when the UDPHS_DMASTATUSx interrupt source is cleared. 1 - set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN. - DMA_6: DMA Channel 6 Interrupt
Value Name Description 0 - reset when the UDPHS_DMASTATUSx interrupt source is cleared. 1 - set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN.
UDPHS UDPHS Clear Interrupt Register
Name: UDPHS_CLRINT
Access: write-only
Address: 0x400A4018
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UPSTR_RES | ENDOFRSM | WAKE_UP | ENDRESET | INT_SOF | MICRO_SOF | DET_SUSPD | - |
- DET_SUSPD: Suspend Interrupt Clear
Value Name Description 0 - no effect. 1 - clear the DET_SUSPD bit in UDPHS_INTSTA. - MICRO_SOF: Micro Start Of Frame Interrupt Clear
Value Name Description 0 - no effect. 1 - clear the MICRO_SOF bit in UDPHS_INTSTA. - INT_SOF: Start Of Frame Interrupt Clear
Value Name Description 0 - no effect. 1 - clear the INT_SOF bit in UDPHS_INTSTA. - ENDRESET: End Of Reset Interrupt Clear
Value Name Description 0 - no effect. 1 - clear the ENDRESET bit in UDPHS_INTSTA. - WAKE_UP: Wake Up CPU Interrupt Clear
Value Name Description 0 - no effect. 1 - clear the WAKE_UP bit in UDPHS_INTSTA. - ENDOFRSM: End Of Resume Interrupt Clear
Value Name Description 0 - no effect. 1 - clear the ENDOFRSM bit in UDPHS_INTSTA. - UPSTR_RES: Upstream Resume Interrupt Clear
Value Name Description 0 - no effect. 1 - clear the UPSTR_RES bit in UDPHS_INTSTA.
UDPHS UDPHS Endpoints Reset Register
Name: UDPHS_EPTRST
Access: write-only
Address: 0x400A401C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | EPT_6 | EPT_5 | EPT_4 | EPT_3 | EPT_2 | EPT_1 | EPT_0 |
- EPT_0: Endpoint 0 Reset
Value Name Description 0 - no effect. 1 - reset the Endpointx state. - EPT_1: Endpoint 1 Reset
Value Name Description 0 - no effect. 1 - reset the Endpointx state. - EPT_2: Endpoint 2 Reset
Value Name Description 0 - no effect. 1 - reset the Endpointx state. - EPT_3: Endpoint 3 Reset
Value Name Description 0 - no effect. 1 - reset the Endpointx state. - EPT_4: Endpoint 4 Reset
Value Name Description 0 - no effect. 1 - reset the Endpointx state. - EPT_5: Endpoint 5 Reset
Value Name Description 0 - no effect. 1 - reset the Endpointx state. - EPT_6: Endpoint 6 Reset
Value Name Description 0 - no effect. 1 - reset the Endpointx state.
UDPHS UDPHS Test Register
Name: UDPHS_TST
Access: read-write
Address: 0x400A40E0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | OPMODE2 | TST_PKT | TST_K | TST_J | SPEED_CFG |
- SPEED_CFG: Speed Configuration
Value Name Description 0x0 NORMAL Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode 0x2 HIGH_SPEED Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. 0x3 FULL_SPEED Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. - TST_J: Test J Mode
Value Name Description 0 - no effect. 1 - set to send the J state on the UDPHS line. This enables the testing of the high output drive level on the D+ line. - TST_K: Test K Mode
Value Name Description 0 - no effect. 1 - set to send the K state on the UDPHS line. This enables the testing of the high output drive level on the D- line. - TST_PKT: Test Packet Mode
Value Name Description 0 - no effect. 1 - set to repetitively transmit the packet stored in the current bank. This enables the testing of rise and fall times, eye pat-terns, jitter, and any other dynamic waveform specifications. - OPMODE2: OpMode2
Value Name Description 0 - no effect. 1 - set to force the OpMode signal (UTMI interface) to "10", to disable the bit-stuffing and the NRZI encoding.
UDPHS UDPHS Name1 Register
Name: UDPHS_IPNAME1
Access: read-only
Address: 0x400A40F0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
IP_NAME1 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IP_NAME1 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IP_NAME1 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IP_NAME1 |
- IP_NAME1
-
UDPHS UDPHS Name2 Register
Name: UDPHS_IPNAME2
Access: read-only
Address: 0x400A40F4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
IP_NAME2 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IP_NAME2 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IP_NAME2 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IP_NAME2 |
- IP_NAME2
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UDPHS UDPHS Features Register
Name: UDPHS_IPFEATURES
Access: read-only
Address: 0x400A40F8
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ISO_EPT_15 | ISO_EPT_14 | ISO_EPT_13 | ISO_EPT_12 | ISO_EPT_11 | ISO_EPT_10 | ISO_EPT_9 | ISO_EPT_8 |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ISO_EPT_7 | ISO_EPT_6 | ISO_EPT_5 | ISO_EPT_4 | ISO_EPT_3 | ISO_EPT_2 | ISO_EPT_1 | DATAB16_8 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BW_DPRAM | FIFO_MAX_SIZE | DMA_FIFO_WORD_DEPTH | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMA_B_SIZ | DMA_CHANNEL_NBR | EPT_NBR_MAX |
- EPT_NBR_MAX: Max Number of Endpoints
- DMA_CHANNEL_NBR: Number of DMA Channels
- DMA_B_SIZ: DMA Buffer Size
Value Name Description 0 - if the DMA Buffer size is 16 bits. 1 - if the DMA Buffer size is 24 bits. - DMA_FIFO_WORD_DEPTH: DMA FIFO Depth in Words
- FIFO_MAX_SIZE: DPRAM Size
Value Name Description 0x0 - if DPRAM is 128 bytes deep. 0x1 - if DPRAM is 256 bytes deep. 0x2 - if DPRAM is 512 bytes deep. 0x3 - if DPRAM is 1024 bytes deep. 0x4 - if DPRAM is 2048 bytes deep. 0x5 - if DPRAM is 4096 bytes deep. 0x6 - if DPRAM is 8192 bytes deep. 0x7 - if DPRAM is 16384 bytes deep. - BW_DPRAM: DPRAM Byte Write Capability
Value Name Description 0 - if DPRAM Write Data Shadow logic is implemented. 1 - if DPRAM is byte write capable. - DATAB16_8: UTMI DataBus16_8
Value Name Description 0 - if the UTMI uses an 8-bit parallel data interface (60 MHz, unidirectional). 1 - if the UTMI uses a 16-bit parallel data interface (30 MHz, bidirectional). - ISO_EPT_1: Endpointx High Bandwidth Isochronous Capability
Value Name Description 0 - if the endpoint does not have isochronous High Bandwidth Capability. 1 - if the endpoint has isochronous High Bandwidth Capability. - ISO_EPT_2: Endpointx High Bandwidth Isochronous Capability
Value Name Description 0 - if the endpoint does not have isochronous High Bandwidth Capability. 1 - if the endpoint has isochronous High Bandwidth Capability. - ISO_EPT_3: Endpointx High Bandwidth Isochronous Capability
Value Name Description 0 - if the endpoint does not have isochronous High Bandwidth Capability. 1 - if the endpoint has isochronous High Bandwidth Capability. - ISO_EPT_4: Endpointx High Bandwidth Isochronous Capability
Value Name Description 0 - if the endpoint does not have isochronous High Bandwidth Capability. 1 - if the endpoint has isochronous High Bandwidth Capability. - ISO_EPT_5: Endpointx High Bandwidth Isochronous Capability
Value Name Description 0 - if the endpoint does not have isochronous High Bandwidth Capability. 1 - if the endpoint has isochronous High Bandwidth Capability. - ISO_EPT_6: Endpointx High Bandwidth Isochronous Capability
Value Name Description 0 - if the endpoint does not have isochronous High Bandwidth Capability. 1 - if the endpoint has isochronous High Bandwidth Capability. - ISO_EPT_7: Endpointx High Bandwidth Isochronous Capability
Value Name Description 0 - if the endpoint does not have isochronous High Bandwidth Capability. 1 - if the endpoint has isochronous High Bandwidth Capability. - ISO_EPT_8: Endpointx High Bandwidth Isochronous Capability
Value Name Description 0 - if the endpoint does not have isochronous High Bandwidth Capability. 1 - if the endpoint has isochronous High Bandwidth Capability. - ISO_EPT_9: Endpointx High Bandwidth Isochronous Capability
Value Name Description 0 - if the endpoint does not have isochronous High Bandwidth Capability. 1 - if the endpoint has isochronous High Bandwidth Capability. - ISO_EPT_10: Endpointx High Bandwidth Isochronous Capability
Value Name Description 0 - if the endpoint does not have isochronous High Bandwidth Capability. 1 - if the endpoint has isochronous High Bandwidth Capability. - ISO_EPT_11: Endpointx High Bandwidth Isochronous Capability
Value Name Description 0 - if the endpoint does not have isochronous High Bandwidth Capability. 1 - if the endpoint has isochronous High Bandwidth Capability. - ISO_EPT_12: Endpointx High Bandwidth Isochronous Capability
Value Name Description 0 - if the endpoint does not have isochronous High Bandwidth Capability. 1 - if the endpoint has isochronous High Bandwidth Capability. - ISO_EPT_13: Endpointx High Bandwidth Isochronous Capability
Value Name Description 0 - if the endpoint does not have isochronous High Bandwidth Capability. 1 - if the endpoint has isochronous High Bandwidth Capability. - ISO_EPT_14: Endpointx High Bandwidth Isochronous Capability
Value Name Description 0 - if the endpoint does not have isochronous High Bandwidth Capability. 1 - if the endpoint has isochronous High Bandwidth Capability. - ISO_EPT_15: Endpointx High Bandwidth Isochronous Capability
Value Name Description 0 - if the endpoint does not have isochronous High Bandwidth Capability. 1 - if the endpoint has isochronous High Bandwidth Capability.
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UDPHS UDPHS Endpoint Configuration Register (endpoint = 0)
Name: UDPHS_EPTCFG0
Access: read-write
Address: 0x400A4100
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
EPT_MAPD | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | NB_TRANS | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BK_NUMBER | EPT_TYPE | EPT_DIR | EPT_SIZE |
- EPT_SIZE: Endpoint Size
Value Name Description 0x0 8 8 bytes 0x1 16 16 bytes 0x2 32 32 bytes 0x3 64 64 bytes 0x4 128 128 bytes 0x5 256 256 bytes 0x6 512 512 bytes 0x7 1024 1024 bytes - EPT_DIR: Endpoint Direction
Value Name Description 0 - Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. 1 - set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. - EPT_TYPE: Endpoint Type
Value Name Description 0x0 CTRL8 Control endpoint 0x1 ISO Isochronous endpoint 0x2 BULK Bulk endpoint 0x3 INT Interrupt endpoint - BK_NUMBER: Number of Banks
Value Name Description 0x0 0 Zero bank, the endpoint is not mapped in memory 0x1 1 One bank (bank 0) 0x2 2 Double bank (Ping-Pong: bank0/bank1) 0x3 3 Triple bank (bank0/bank1/bank2) - NB_TRANS: Number Of Transaction per Microframe
- EPT_MAPD: Endpoint Mapped
Value Name Description 0 - the user should reprogram the register with correct values. 1 - set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding:
-
UDPHS UDPHS Endpoint Control Enable Register (endpoint = 0)
Name: UDPHS_EPTCTLENB0
Access: write-only
Address: 0x400A4104
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_ENABL |
- EPT_ENABL: Endpoint Enable
Value Name Description 0 - no effect. 1 - enable endpoint according to the device configuration. - AUTO_VALID: Packet Auto-Valid Enable
Value Name Description 0 - no effect. 1 - enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers. - INTDIS_DMA: Interrupts Disable DMA
Value Name Description 0 - no effect. 1 - If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled. - NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - no effect. 1 - forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. - DATAX_RX: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - enable DATAx Interrupt. - MDATA_RX: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - enable MDATA Interrupt. - ERR_OVFLW: Overflow Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Overflow Error Interrupt. - RX_BK_RDY: Received OUT Data Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Received OUT Data Interrupt. - TX_COMPLT: Transmitted IN Data Complete Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Transmitted IN Data Complete Interrupt. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable TX Packet Ready/Transaction Error Interrupt. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable TX Packet Ready/Transaction Error Interrupt. - RX_SETUP: Received SETUP/Error Flow Interrupt Enable
Value Name Description 0 - no effect. 1 - enable RX_SETUP/Error Flow ISO Interrupt. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enable
Value Name Description 0 - no effect. 1 - enable RX_SETUP/Error Flow ISO Interrupt. - STALL_SNT: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_CRISO: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_NBTRA: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - NAK_IN: NAKIN/Bank Flush Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKIN/Bank Flush Error Interrupt. - ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKIN/Bank Flush Error Interrupt. - NAK_OUT: NAKOUT Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKOUT Interrupt. - BUSY_BANK: Busy Bank Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Busy Bank Interrupt. - SHRT_PCKT: Short Packet Send/Short Packet Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Short Packet Interrupt.
UDPHS UDPHS Endpoint Control Disable Register (endpoint = 0)
Name: UDPHS_EPTCTLDIS0
Access: write-only
Address: 0x400A4108
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_DISABL |
- EPT_DISABL: Endpoint Disable
Value Name Description 0 - no effect. 1 - disable endpoint. - AUTO_VALID: Packet Auto-Valid Disable
Value Name Description 0 - no effect. 1 - disable this bit to not automatically validate the current packet. - INTDIS_DMA: Interrupts Disable DMA
Value Name Description 0 - no effect. 1 - disable the "Interrupts Disable DMA". - NYET_DIS: NYET Enable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - no effect. 1 - let the hardware handle the handshake response for the High Speed Bulk OUT transfer. - DATAX_RX: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - disable DATAx Interrupt. - MDATA_RX: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - disable MDATA Interrupt. - ERR_OVFLW: Overflow Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Overflow Error Interrupt. - RX_BK_RDY: Received OUT Data Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Received OUT Data Interrupt. - TX_COMPLT: Transmitted IN Data Complete Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Transmitted IN Data Complete Interrupt. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable TX Packet Ready/Transaction Error Interrupt. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable TX Packet Ready/Transaction Error Interrupt. - RX_SETUP: Received SETUP/Error Flow Interrupt Disable
Value Name Description 0 - no effect. 1 - disable RX_SETUP/Error Flow ISO Interrupt. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Disable
Value Name Description 0 - no effect. 1 - disable RX_SETUP/Error Flow ISO Interrupt. - STALL_SNT: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_CRISO: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - NAK_IN: NAKIN/bank flush error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKIN/ Bank Flush Error Interrupt. - ERR_FLUSH: NAKIN/bank flush error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKIN/ Bank Flush Error Interrupt. - NAK_OUT: NAKOUT Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKOUT Interrupt. - BUSY_BANK: Busy Bank Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Busy Bank Interrupt. - SHRT_PCKT: Short Packet Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Short Packet Interrupt.
UDPHS UDPHS Endpoint Control Register (endpoint = 0)
Name: UDPHS_EPTCTL0
Access: read-only
Address: 0x400A410C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_ENABL |
- EPT_ENABL: Endpoint Enable
Value Name Description 0 - If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration. 1 - If set, the endpoint is enabled according to the device configuration. - AUTO_VALID: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
- INTDIS_DMA: Interrupt Disables DMA
- NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - If clear, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer. 1 - If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. - DATAX_RX: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received. - MDATA_RX: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data pay-load has been received. - ERR_OVFLW: Overflow Error Interrupt Enabled
Value Name Description 0 - Overflow Error Interrupt is masked. 1 - Overflow Error Interrupt is enabled. - RX_BK_RDY: Received OUT Data Interrupt Enabled
Value Name Description 0 - Received OUT Data Interrupt is masked. 1 - Received OUT Data Interrupt is enabled. - TX_COMPLT: Transmitted IN Data Complete Interrupt Enabled
Value Name Description 0 - Transmitted IN Data Complete Interrupt is masked. 1 - Transmitted IN Data Complete Interrupt is enabled. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Enabled
Value Name Description 0 - TX Packet Ready/Transaction Error Interrupt is masked. 1 - TX Packet Ready/Transaction Error Interrupt is enabled. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enabled
Value Name Description 0 - TX Packet Ready/Transaction Error Interrupt is masked. 1 - TX Packet Ready/Transaction Error Interrupt is enabled. - RX_SETUP: Received SETUP/Error Flow Interrupt Enabled
Value Name Description 0 - Received SETUP/Error Flow Interrupt is masked. 1 - Received SETUP/Error Flow Interrupt is enabled. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enabled
Value Name Description 0 - Received SETUP/Error Flow Interrupt is masked. 1 - Received SETUP/Error Flow Interrupt is enabled. - STALL_SNT: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - ERR_CRISO: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - NAK_IN: NAKIN/Bank Flush Error Interrupt Enabled
Value Name Description 0 - NAKIN Interrupt is masked. 1 - NAKIN/Bank Flush Error Interrupt is enabled. - ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enabled
Value Name Description 0 - NAKIN Interrupt is masked. 1 - NAKIN/Bank Flush Error Interrupt is enabled. - NAK_OUT: NAKOUT Interrupt Enabled
Value Name Description 0 - NAKOUT Interrupt is masked. 1 - NAKOUT Interrupt is enabled. - BUSY_BANK: Busy Bank Interrupt Enabled
Value Name Description 0 - BUSY_BANK Interrupt is masked. 1 - BUSY_BANK Interrupt is enabled. - SHRT_PCKT: Short Packet Interrupt Enabled
Value Name Description 0 - Short Packet Interrupt is masked. 1 - Short Packet Interrupt is enabled.
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UDPHS UDPHS Endpoint Set Status Register (endpoint = 0)
Name: UDPHS_EPTSETSTA0
Access: write-only
Address: 0x400A4114
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | TX_PK_RDY | - | KILL_BANK | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request Set
Value Name Description 0 - no effect. 1 - set this bit to request a STALL answer to the host for the next handshake - KILL_BANK: KILL Bank Set (for IN Endpoint)
Value Name Description 0 - no effect. 1 - kill the last written bank. - TX_PK_RDY: TX Packet Ready Set
Value Name Description 0 - no effect. 1 - set this bit after a packet has been written into the endpoint FIFO for IN data transfers
UDPHS UDPHS Endpoint Clear Status Register (endpoint = 0)
Name: UDPHS_EPTCLRSTA0
Access: write-only
Address: 0x400A4118
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | - | TX_COMPLT | RX_BK_RDY | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | TOGGLESQ | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request Clear
Value Name Description 0 - no effect. 1 - clear the STALL request. The next packets from host will not be STALLed. - TOGGLESQ: Data Toggle Clear
Value Name Description 0 - no effect. 1 - clear the PID data of the current bank - RX_BK_RDY: Received OUT Data Clear
Value Name Description 0 - no effect. 1 - clear the RX_BK_RDY flag of UDPHS_EPTSTAx. - TX_COMPLT: Transmitted IN Data Complete Clear
Value Name Description 0 - no effect. 1 - clear the TX_COMPLT flag of UDPHS_EPTSTAx. - RX_SETUP: Received SETUP/Error Flow Clear
Value Name Description 0 - no effect. 1 - clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx. - ERR_FL_ISO: Received SETUP/Error Flow Clear
Value Name Description 0 - no effect. 1 - clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx. - STALL_SNT: Stall Sent/Number of Transaction Error Clear
Value Name Description 0 - no effect. 1 - clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx. - ERR_NBTRA: Stall Sent/Number of Transaction Error Clear
Value Name Description 0 - no effect. 1 - clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx. - NAK_IN: NAKIN/Bank Flush Error Clear
Value Name Description 0 - no effect. 1 - clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. - ERR_FLUSH: NAKIN/Bank Flush Error Clear
Value Name Description 0 - no effect. 1 - clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. - NAK_OUT: NAKOUT Clear
Value Name Description 0 - no effect. 1 - clear the NAK_OUT flag of UDPHS_EPTSTAx.
UDPHS UDPHS Endpoint Status Register (endpoint = 0)
Name: UDPHS_EPTSTA0
Access: read-only
Address: 0x400A411C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | BYTE_COUNT | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BYTE_COUNT | BUSY_BANK_STA | CURRENT_BANK | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOGGLESQ_STA | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request
Value Name Description 0 - no effect. 1 - If set a STALL answer will be done to the host for the next handshake. - TOGGLESQ_STA: Toggle Sequencing
Value Name Description 0x0 DATA0 DATA0 0x1 DATA1 DATA1 0x2 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x3 MDATA MData (only for High Bandwidth Isochronous Endpoint) - ERR_OVFLW: Overflow Error
- RX_BK_RDY: Received OUT Data/KILL Bank
- KILL_BANK: Received OUT Data/KILL Bank
- TX_COMPLT: Transmitted IN Data Complete
- TX_PK_RDY: TX Packet Ready/Transaction Error
- ERR_TRANS: TX Packet Ready/Transaction Error
- RX_SETUP: Received SETUP/Error Flow
- ERR_FL_ISO: Received SETUP/Error Flow
- STALL_SNT: Stall Sent/CRC ISO Error/Number of Transaction Error
- ERR_CRISO: Stall Sent/CRC ISO Error/Number of Transaction Error
- ERR_NBTRA: Stall Sent/CRC ISO Error/Number of Transaction Error
- NAK_IN: NAK IN/Bank Flush Error
- ERR_FLUSH: NAK IN/Bank Flush Error
- NAK_OUT: NAK OUT
- CURRENT_BANK: Current Bank/Control Direction
- CONTROL_DIR: Current Bank/Control Direction
- BUSY_BANK_STA: Busy Bank Number
Value Name Description 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks - BYTE_COUNT: UDPHS Byte Count
- SHRT_PCKT: Short Packet
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UDPHS UDPHS Endpoint Configuration Register (endpoint = 1)
Name: UDPHS_EPTCFG1
Access: read-write
Address: 0x400A4120
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
EPT_MAPD | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | NB_TRANS | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BK_NUMBER | EPT_TYPE | EPT_DIR | EPT_SIZE |
- EPT_SIZE: Endpoint Size
Value Name Description 0x0 8 8 bytes 0x1 16 16 bytes 0x2 32 32 bytes 0x3 64 64 bytes 0x4 128 128 bytes 0x5 256 256 bytes 0x6 512 512 bytes 0x7 1024 1024 bytes - EPT_DIR: Endpoint Direction
Value Name Description 0 - Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. 1 - set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. - EPT_TYPE: Endpoint Type
Value Name Description 0x0 CTRL8 Control endpoint 0x1 ISO Isochronous endpoint 0x2 BULK Bulk endpoint 0x3 INT Interrupt endpoint - BK_NUMBER: Number of Banks
Value Name Description 0x0 0 Zero bank, the endpoint is not mapped in memory 0x1 1 One bank (bank 0) 0x2 2 Double bank (Ping-Pong: bank0/bank1) 0x3 3 Triple bank (bank0/bank1/bank2) - NB_TRANS: Number Of Transaction per Microframe
- EPT_MAPD: Endpoint Mapped
Value Name Description 0 - the user should reprogram the register with correct values. 1 - set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding:
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UDPHS UDPHS Endpoint Control Enable Register (endpoint = 1)
Name: UDPHS_EPTCTLENB1
Access: write-only
Address: 0x400A4124
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_ENABL |
- EPT_ENABL: Endpoint Enable
Value Name Description 0 - no effect. 1 - enable endpoint according to the device configuration. - AUTO_VALID: Packet Auto-Valid Enable
Value Name Description 0 - no effect. 1 - enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers. - INTDIS_DMA: Interrupts Disable DMA
Value Name Description 0 - no effect. 1 - If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled. - NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - no effect. 1 - forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. - DATAX_RX: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - enable DATAx Interrupt. - MDATA_RX: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - enable MDATA Interrupt. - ERR_OVFLW: Overflow Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Overflow Error Interrupt. - RX_BK_RDY: Received OUT Data Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Received OUT Data Interrupt. - TX_COMPLT: Transmitted IN Data Complete Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Transmitted IN Data Complete Interrupt. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable TX Packet Ready/Transaction Error Interrupt. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable TX Packet Ready/Transaction Error Interrupt. - RX_SETUP: Received SETUP/Error Flow Interrupt Enable
Value Name Description 0 - no effect. 1 - enable RX_SETUP/Error Flow ISO Interrupt. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enable
Value Name Description 0 - no effect. 1 - enable RX_SETUP/Error Flow ISO Interrupt. - STALL_SNT: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_CRISO: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_NBTRA: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - NAK_IN: NAKIN/Bank Flush Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKIN/Bank Flush Error Interrupt. - ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKIN/Bank Flush Error Interrupt. - NAK_OUT: NAKOUT Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKOUT Interrupt. - BUSY_BANK: Busy Bank Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Busy Bank Interrupt. - SHRT_PCKT: Short Packet Send/Short Packet Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Short Packet Interrupt.
UDPHS UDPHS Endpoint Control Disable Register (endpoint = 1)
Name: UDPHS_EPTCTLDIS1
Access: write-only
Address: 0x400A4128
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_DISABL |
- EPT_DISABL: Endpoint Disable
Value Name Description 0 - no effect. 1 - disable endpoint. - AUTO_VALID: Packet Auto-Valid Disable
Value Name Description 0 - no effect. 1 - disable this bit to not automatically validate the current packet. - INTDIS_DMA: Interrupts Disable DMA
Value Name Description 0 - no effect. 1 - disable the "Interrupts Disable DMA". - NYET_DIS: NYET Enable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - no effect. 1 - let the hardware handle the handshake response for the High Speed Bulk OUT transfer. - DATAX_RX: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - disable DATAx Interrupt. - MDATA_RX: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - disable MDATA Interrupt. - ERR_OVFLW: Overflow Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Overflow Error Interrupt. - RX_BK_RDY: Received OUT Data Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Received OUT Data Interrupt. - TX_COMPLT: Transmitted IN Data Complete Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Transmitted IN Data Complete Interrupt. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable TX Packet Ready/Transaction Error Interrupt. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable TX Packet Ready/Transaction Error Interrupt. - RX_SETUP: Received SETUP/Error Flow Interrupt Disable
Value Name Description 0 - no effect. 1 - disable RX_SETUP/Error Flow ISO Interrupt. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Disable
Value Name Description 0 - no effect. 1 - disable RX_SETUP/Error Flow ISO Interrupt. - STALL_SNT: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_CRISO: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - NAK_IN: NAKIN/bank flush error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKIN/ Bank Flush Error Interrupt. - ERR_FLUSH: NAKIN/bank flush error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKIN/ Bank Flush Error Interrupt. - NAK_OUT: NAKOUT Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKOUT Interrupt. - BUSY_BANK: Busy Bank Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Busy Bank Interrupt. - SHRT_PCKT: Short Packet Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Short Packet Interrupt.
UDPHS UDPHS Endpoint Control Register (endpoint = 1)
Name: UDPHS_EPTCTL1
Access: read-only
Address: 0x400A412C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_ENABL |
- EPT_ENABL: Endpoint Enable
Value Name Description 0 - If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration. 1 - If set, the endpoint is enabled according to the device configuration. - AUTO_VALID: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
- INTDIS_DMA: Interrupt Disables DMA
- NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - If clear, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer. 1 - If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. - DATAX_RX: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received. - MDATA_RX: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data pay-load has been received. - ERR_OVFLW: Overflow Error Interrupt Enabled
Value Name Description 0 - Overflow Error Interrupt is masked. 1 - Overflow Error Interrupt is enabled. - RX_BK_RDY: Received OUT Data Interrupt Enabled
Value Name Description 0 - Received OUT Data Interrupt is masked. 1 - Received OUT Data Interrupt is enabled. - TX_COMPLT: Transmitted IN Data Complete Interrupt Enabled
Value Name Description 0 - Transmitted IN Data Complete Interrupt is masked. 1 - Transmitted IN Data Complete Interrupt is enabled. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Enabled
Value Name Description 0 - TX Packet Ready/Transaction Error Interrupt is masked. 1 - TX Packet Ready/Transaction Error Interrupt is enabled. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enabled
Value Name Description 0 - TX Packet Ready/Transaction Error Interrupt is masked. 1 - TX Packet Ready/Transaction Error Interrupt is enabled. - RX_SETUP: Received SETUP/Error Flow Interrupt Enabled
Value Name Description 0 - Received SETUP/Error Flow Interrupt is masked. 1 - Received SETUP/Error Flow Interrupt is enabled. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enabled
Value Name Description 0 - Received SETUP/Error Flow Interrupt is masked. 1 - Received SETUP/Error Flow Interrupt is enabled. - STALL_SNT: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - ERR_CRISO: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - NAK_IN: NAKIN/Bank Flush Error Interrupt Enabled
Value Name Description 0 - NAKIN Interrupt is masked. 1 - NAKIN/Bank Flush Error Interrupt is enabled. - ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enabled
Value Name Description 0 - NAKIN Interrupt is masked. 1 - NAKIN/Bank Flush Error Interrupt is enabled. - NAK_OUT: NAKOUT Interrupt Enabled
Value Name Description 0 - NAKOUT Interrupt is masked. 1 - NAKOUT Interrupt is enabled. - BUSY_BANK: Busy Bank Interrupt Enabled
Value Name Description 0 - BUSY_BANK Interrupt is masked. 1 - BUSY_BANK Interrupt is enabled. - SHRT_PCKT: Short Packet Interrupt Enabled
Value Name Description 0 - Short Packet Interrupt is masked. 1 - Short Packet Interrupt is enabled.
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UDPHS UDPHS Endpoint Set Status Register (endpoint = 1)
Name: UDPHS_EPTSETSTA1
Access: write-only
Address: 0x400A4134
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | TX_PK_RDY | - | KILL_BANK | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request Set
Value Name Description 0 - no effect. 1 - set this bit to request a STALL answer to the host for the next handshake - KILL_BANK: KILL Bank Set (for IN Endpoint)
Value Name Description 0 - no effect. 1 - kill the last written bank. - TX_PK_RDY: TX Packet Ready Set
Value Name Description 0 - no effect. 1 - set this bit after a packet has been written into the endpoint FIFO for IN data transfers
UDPHS UDPHS Endpoint Clear Status Register (endpoint = 1)
Name: UDPHS_EPTCLRSTA1
Access: write-only
Address: 0x400A4138
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | - | TX_COMPLT | RX_BK_RDY | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | TOGGLESQ | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request Clear
Value Name Description 0 - no effect. 1 - clear the STALL request. The next packets from host will not be STALLed. - TOGGLESQ: Data Toggle Clear
Value Name Description 0 - no effect. 1 - clear the PID data of the current bank - RX_BK_RDY: Received OUT Data Clear
Value Name Description 0 - no effect. 1 - clear the RX_BK_RDY flag of UDPHS_EPTSTAx. - TX_COMPLT: Transmitted IN Data Complete Clear
Value Name Description 0 - no effect. 1 - clear the TX_COMPLT flag of UDPHS_EPTSTAx. - RX_SETUP: Received SETUP/Error Flow Clear
Value Name Description 0 - no effect. 1 - clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx. - ERR_FL_ISO: Received SETUP/Error Flow Clear
Value Name Description 0 - no effect. 1 - clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx. - STALL_SNT: Stall Sent/Number of Transaction Error Clear
Value Name Description 0 - no effect. 1 - clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx. - ERR_NBTRA: Stall Sent/Number of Transaction Error Clear
Value Name Description 0 - no effect. 1 - clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx. - NAK_IN: NAKIN/Bank Flush Error Clear
Value Name Description 0 - no effect. 1 - clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. - ERR_FLUSH: NAKIN/Bank Flush Error Clear
Value Name Description 0 - no effect. 1 - clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. - NAK_OUT: NAKOUT Clear
Value Name Description 0 - no effect. 1 - clear the NAK_OUT flag of UDPHS_EPTSTAx.
UDPHS UDPHS Endpoint Status Register (endpoint = 1)
Name: UDPHS_EPTSTA1
Access: read-only
Address: 0x400A413C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | BYTE_COUNT | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BYTE_COUNT | BUSY_BANK_STA | CURRENT_BANK | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOGGLESQ_STA | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request
Value Name Description 0 - no effect. 1 - If set a STALL answer will be done to the host for the next handshake. - TOGGLESQ_STA: Toggle Sequencing
Value Name Description 0x0 DATA0 DATA0 0x1 DATA1 DATA1 0x2 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x3 MDATA MData (only for High Bandwidth Isochronous Endpoint) - ERR_OVFLW: Overflow Error
- RX_BK_RDY: Received OUT Data/KILL Bank
- KILL_BANK: Received OUT Data/KILL Bank
- TX_COMPLT: Transmitted IN Data Complete
- TX_PK_RDY: TX Packet Ready/Transaction Error
- ERR_TRANS: TX Packet Ready/Transaction Error
- RX_SETUP: Received SETUP/Error Flow
- ERR_FL_ISO: Received SETUP/Error Flow
- STALL_SNT: Stall Sent/CRC ISO Error/Number of Transaction Error
- ERR_CRISO: Stall Sent/CRC ISO Error/Number of Transaction Error
- ERR_NBTRA: Stall Sent/CRC ISO Error/Number of Transaction Error
- NAK_IN: NAK IN/Bank Flush Error
- ERR_FLUSH: NAK IN/Bank Flush Error
- NAK_OUT: NAK OUT
- CURRENT_BANK: Current Bank/Control Direction
- CONTROL_DIR: Current Bank/Control Direction
- BUSY_BANK_STA: Busy Bank Number
Value Name Description 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks - BYTE_COUNT: UDPHS Byte Count
- SHRT_PCKT: Short Packet
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UDPHS UDPHS Endpoint Configuration Register (endpoint = 2)
Name: UDPHS_EPTCFG2
Access: read-write
Address: 0x400A4140
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
EPT_MAPD | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | NB_TRANS | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BK_NUMBER | EPT_TYPE | EPT_DIR | EPT_SIZE |
- EPT_SIZE: Endpoint Size
Value Name Description 0x0 8 8 bytes 0x1 16 16 bytes 0x2 32 32 bytes 0x3 64 64 bytes 0x4 128 128 bytes 0x5 256 256 bytes 0x6 512 512 bytes 0x7 1024 1024 bytes - EPT_DIR: Endpoint Direction
Value Name Description 0 - Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. 1 - set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. - EPT_TYPE: Endpoint Type
Value Name Description 0x0 CTRL8 Control endpoint 0x1 ISO Isochronous endpoint 0x2 BULK Bulk endpoint 0x3 INT Interrupt endpoint - BK_NUMBER: Number of Banks
Value Name Description 0x0 0 Zero bank, the endpoint is not mapped in memory 0x1 1 One bank (bank 0) 0x2 2 Double bank (Ping-Pong: bank0/bank1) 0x3 3 Triple bank (bank0/bank1/bank2) - NB_TRANS: Number Of Transaction per Microframe
- EPT_MAPD: Endpoint Mapped
Value Name Description 0 - the user should reprogram the register with correct values. 1 - set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding:
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UDPHS UDPHS Endpoint Control Enable Register (endpoint = 2)
Name: UDPHS_EPTCTLENB2
Access: write-only
Address: 0x400A4144
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_ENABL |
- EPT_ENABL: Endpoint Enable
Value Name Description 0 - no effect. 1 - enable endpoint according to the device configuration. - AUTO_VALID: Packet Auto-Valid Enable
Value Name Description 0 - no effect. 1 - enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers. - INTDIS_DMA: Interrupts Disable DMA
Value Name Description 0 - no effect. 1 - If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled. - NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - no effect. 1 - forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. - DATAX_RX: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - enable DATAx Interrupt. - MDATA_RX: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - enable MDATA Interrupt. - ERR_OVFLW: Overflow Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Overflow Error Interrupt. - RX_BK_RDY: Received OUT Data Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Received OUT Data Interrupt. - TX_COMPLT: Transmitted IN Data Complete Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Transmitted IN Data Complete Interrupt. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable TX Packet Ready/Transaction Error Interrupt. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable TX Packet Ready/Transaction Error Interrupt. - RX_SETUP: Received SETUP/Error Flow Interrupt Enable
Value Name Description 0 - no effect. 1 - enable RX_SETUP/Error Flow ISO Interrupt. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enable
Value Name Description 0 - no effect. 1 - enable RX_SETUP/Error Flow ISO Interrupt. - STALL_SNT: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_CRISO: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_NBTRA: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - NAK_IN: NAKIN/Bank Flush Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKIN/Bank Flush Error Interrupt. - ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKIN/Bank Flush Error Interrupt. - NAK_OUT: NAKOUT Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKOUT Interrupt. - BUSY_BANK: Busy Bank Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Busy Bank Interrupt. - SHRT_PCKT: Short Packet Send/Short Packet Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Short Packet Interrupt.
UDPHS UDPHS Endpoint Control Disable Register (endpoint = 2)
Name: UDPHS_EPTCTLDIS2
Access: write-only
Address: 0x400A4148
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_DISABL |
- EPT_DISABL: Endpoint Disable
Value Name Description 0 - no effect. 1 - disable endpoint. - AUTO_VALID: Packet Auto-Valid Disable
Value Name Description 0 - no effect. 1 - disable this bit to not automatically validate the current packet. - INTDIS_DMA: Interrupts Disable DMA
Value Name Description 0 - no effect. 1 - disable the "Interrupts Disable DMA". - NYET_DIS: NYET Enable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - no effect. 1 - let the hardware handle the handshake response for the High Speed Bulk OUT transfer. - DATAX_RX: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - disable DATAx Interrupt. - MDATA_RX: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - disable MDATA Interrupt. - ERR_OVFLW: Overflow Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Overflow Error Interrupt. - RX_BK_RDY: Received OUT Data Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Received OUT Data Interrupt. - TX_COMPLT: Transmitted IN Data Complete Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Transmitted IN Data Complete Interrupt. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable TX Packet Ready/Transaction Error Interrupt. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable TX Packet Ready/Transaction Error Interrupt. - RX_SETUP: Received SETUP/Error Flow Interrupt Disable
Value Name Description 0 - no effect. 1 - disable RX_SETUP/Error Flow ISO Interrupt. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Disable
Value Name Description 0 - no effect. 1 - disable RX_SETUP/Error Flow ISO Interrupt. - STALL_SNT: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_CRISO: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - NAK_IN: NAKIN/bank flush error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKIN/ Bank Flush Error Interrupt. - ERR_FLUSH: NAKIN/bank flush error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKIN/ Bank Flush Error Interrupt. - NAK_OUT: NAKOUT Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKOUT Interrupt. - BUSY_BANK: Busy Bank Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Busy Bank Interrupt. - SHRT_PCKT: Short Packet Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Short Packet Interrupt.
UDPHS UDPHS Endpoint Control Register (endpoint = 2)
Name: UDPHS_EPTCTL2
Access: read-only
Address: 0x400A414C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_ENABL |
- EPT_ENABL: Endpoint Enable
Value Name Description 0 - If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration. 1 - If set, the endpoint is enabled according to the device configuration. - AUTO_VALID: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
- INTDIS_DMA: Interrupt Disables DMA
- NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - If clear, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer. 1 - If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. - DATAX_RX: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received. - MDATA_RX: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data pay-load has been received. - ERR_OVFLW: Overflow Error Interrupt Enabled
Value Name Description 0 - Overflow Error Interrupt is masked. 1 - Overflow Error Interrupt is enabled. - RX_BK_RDY: Received OUT Data Interrupt Enabled
Value Name Description 0 - Received OUT Data Interrupt is masked. 1 - Received OUT Data Interrupt is enabled. - TX_COMPLT: Transmitted IN Data Complete Interrupt Enabled
Value Name Description 0 - Transmitted IN Data Complete Interrupt is masked. 1 - Transmitted IN Data Complete Interrupt is enabled. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Enabled
Value Name Description 0 - TX Packet Ready/Transaction Error Interrupt is masked. 1 - TX Packet Ready/Transaction Error Interrupt is enabled. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enabled
Value Name Description 0 - TX Packet Ready/Transaction Error Interrupt is masked. 1 - TX Packet Ready/Transaction Error Interrupt is enabled. - RX_SETUP: Received SETUP/Error Flow Interrupt Enabled
Value Name Description 0 - Received SETUP/Error Flow Interrupt is masked. 1 - Received SETUP/Error Flow Interrupt is enabled. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enabled
Value Name Description 0 - Received SETUP/Error Flow Interrupt is masked. 1 - Received SETUP/Error Flow Interrupt is enabled. - STALL_SNT: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - ERR_CRISO: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - NAK_IN: NAKIN/Bank Flush Error Interrupt Enabled
Value Name Description 0 - NAKIN Interrupt is masked. 1 - NAKIN/Bank Flush Error Interrupt is enabled. - ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enabled
Value Name Description 0 - NAKIN Interrupt is masked. 1 - NAKIN/Bank Flush Error Interrupt is enabled. - NAK_OUT: NAKOUT Interrupt Enabled
Value Name Description 0 - NAKOUT Interrupt is masked. 1 - NAKOUT Interrupt is enabled. - BUSY_BANK: Busy Bank Interrupt Enabled
Value Name Description 0 - BUSY_BANK Interrupt is masked. 1 - BUSY_BANK Interrupt is enabled. - SHRT_PCKT: Short Packet Interrupt Enabled
Value Name Description 0 - Short Packet Interrupt is masked. 1 - Short Packet Interrupt is enabled.
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UDPHS UDPHS Endpoint Set Status Register (endpoint = 2)
Name: UDPHS_EPTSETSTA2
Access: write-only
Address: 0x400A4154
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | TX_PK_RDY | - | KILL_BANK | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request Set
Value Name Description 0 - no effect. 1 - set this bit to request a STALL answer to the host for the next handshake - KILL_BANK: KILL Bank Set (for IN Endpoint)
Value Name Description 0 - no effect. 1 - kill the last written bank. - TX_PK_RDY: TX Packet Ready Set
Value Name Description 0 - no effect. 1 - set this bit after a packet has been written into the endpoint FIFO for IN data transfers
UDPHS UDPHS Endpoint Clear Status Register (endpoint = 2)
Name: UDPHS_EPTCLRSTA2
Access: write-only
Address: 0x400A4158
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | - | TX_COMPLT | RX_BK_RDY | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | TOGGLESQ | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request Clear
Value Name Description 0 - no effect. 1 - clear the STALL request. The next packets from host will not be STALLed. - TOGGLESQ: Data Toggle Clear
Value Name Description 0 - no effect. 1 - clear the PID data of the current bank - RX_BK_RDY: Received OUT Data Clear
Value Name Description 0 - no effect. 1 - clear the RX_BK_RDY flag of UDPHS_EPTSTAx. - TX_COMPLT: Transmitted IN Data Complete Clear
Value Name Description 0 - no effect. 1 - clear the TX_COMPLT flag of UDPHS_EPTSTAx. - RX_SETUP: Received SETUP/Error Flow Clear
Value Name Description 0 - no effect. 1 - clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx. - ERR_FL_ISO: Received SETUP/Error Flow Clear
Value Name Description 0 - no effect. 1 - clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx. - STALL_SNT: Stall Sent/Number of Transaction Error Clear
Value Name Description 0 - no effect. 1 - clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx. - ERR_NBTRA: Stall Sent/Number of Transaction Error Clear
Value Name Description 0 - no effect. 1 - clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx. - NAK_IN: NAKIN/Bank Flush Error Clear
Value Name Description 0 - no effect. 1 - clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. - ERR_FLUSH: NAKIN/Bank Flush Error Clear
Value Name Description 0 - no effect. 1 - clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. - NAK_OUT: NAKOUT Clear
Value Name Description 0 - no effect. 1 - clear the NAK_OUT flag of UDPHS_EPTSTAx.
UDPHS UDPHS Endpoint Status Register (endpoint = 2)
Name: UDPHS_EPTSTA2
Access: read-only
Address: 0x400A415C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | BYTE_COUNT | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BYTE_COUNT | BUSY_BANK_STA | CURRENT_BANK | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOGGLESQ_STA | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request
Value Name Description 0 - no effect. 1 - If set a STALL answer will be done to the host for the next handshake. - TOGGLESQ_STA: Toggle Sequencing
Value Name Description 0x0 DATA0 DATA0 0x1 DATA1 DATA1 0x2 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x3 MDATA MData (only for High Bandwidth Isochronous Endpoint) - ERR_OVFLW: Overflow Error
- RX_BK_RDY: Received OUT Data/KILL Bank
- KILL_BANK: Received OUT Data/KILL Bank
- TX_COMPLT: Transmitted IN Data Complete
- TX_PK_RDY: TX Packet Ready/Transaction Error
- ERR_TRANS: TX Packet Ready/Transaction Error
- RX_SETUP: Received SETUP/Error Flow
- ERR_FL_ISO: Received SETUP/Error Flow
- STALL_SNT: Stall Sent/CRC ISO Error/Number of Transaction Error
- ERR_CRISO: Stall Sent/CRC ISO Error/Number of Transaction Error
- ERR_NBTRA: Stall Sent/CRC ISO Error/Number of Transaction Error
- NAK_IN: NAK IN/Bank Flush Error
- ERR_FLUSH: NAK IN/Bank Flush Error
- NAK_OUT: NAK OUT
- CURRENT_BANK: Current Bank/Control Direction
- CONTROL_DIR: Current Bank/Control Direction
- BUSY_BANK_STA: Busy Bank Number
Value Name Description 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks - BYTE_COUNT: UDPHS Byte Count
- SHRT_PCKT: Short Packet
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UDPHS UDPHS Endpoint Configuration Register (endpoint = 3)
Name: UDPHS_EPTCFG3
Access: read-write
Address: 0x400A4160
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
EPT_MAPD | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | NB_TRANS | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BK_NUMBER | EPT_TYPE | EPT_DIR | EPT_SIZE |
- EPT_SIZE: Endpoint Size
Value Name Description 0x0 8 8 bytes 0x1 16 16 bytes 0x2 32 32 bytes 0x3 64 64 bytes 0x4 128 128 bytes 0x5 256 256 bytes 0x6 512 512 bytes 0x7 1024 1024 bytes - EPT_DIR: Endpoint Direction
Value Name Description 0 - Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. 1 - set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. - EPT_TYPE: Endpoint Type
Value Name Description 0x0 CTRL8 Control endpoint 0x1 ISO Isochronous endpoint 0x2 BULK Bulk endpoint 0x3 INT Interrupt endpoint - BK_NUMBER: Number of Banks
Value Name Description 0x0 0 Zero bank, the endpoint is not mapped in memory 0x1 1 One bank (bank 0) 0x2 2 Double bank (Ping-Pong: bank0/bank1) 0x3 3 Triple bank (bank0/bank1/bank2) - NB_TRANS: Number Of Transaction per Microframe
- EPT_MAPD: Endpoint Mapped
Value Name Description 0 - the user should reprogram the register with correct values. 1 - set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding:
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UDPHS UDPHS Endpoint Control Enable Register (endpoint = 3)
Name: UDPHS_EPTCTLENB3
Access: write-only
Address: 0x400A4164
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_ENABL |
- EPT_ENABL: Endpoint Enable
Value Name Description 0 - no effect. 1 - enable endpoint according to the device configuration. - AUTO_VALID: Packet Auto-Valid Enable
Value Name Description 0 - no effect. 1 - enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers. - INTDIS_DMA: Interrupts Disable DMA
Value Name Description 0 - no effect. 1 - If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled. - NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - no effect. 1 - forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. - DATAX_RX: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - enable DATAx Interrupt. - MDATA_RX: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - enable MDATA Interrupt. - ERR_OVFLW: Overflow Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Overflow Error Interrupt. - RX_BK_RDY: Received OUT Data Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Received OUT Data Interrupt. - TX_COMPLT: Transmitted IN Data Complete Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Transmitted IN Data Complete Interrupt. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable TX Packet Ready/Transaction Error Interrupt. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable TX Packet Ready/Transaction Error Interrupt. - RX_SETUP: Received SETUP/Error Flow Interrupt Enable
Value Name Description 0 - no effect. 1 - enable RX_SETUP/Error Flow ISO Interrupt. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enable
Value Name Description 0 - no effect. 1 - enable RX_SETUP/Error Flow ISO Interrupt. - STALL_SNT: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_CRISO: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_NBTRA: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - NAK_IN: NAKIN/Bank Flush Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKIN/Bank Flush Error Interrupt. - ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKIN/Bank Flush Error Interrupt. - NAK_OUT: NAKOUT Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKOUT Interrupt. - BUSY_BANK: Busy Bank Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Busy Bank Interrupt. - SHRT_PCKT: Short Packet Send/Short Packet Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Short Packet Interrupt.
UDPHS UDPHS Endpoint Control Disable Register (endpoint = 3)
Name: UDPHS_EPTCTLDIS3
Access: write-only
Address: 0x400A4168
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_DISABL |
- EPT_DISABL: Endpoint Disable
Value Name Description 0 - no effect. 1 - disable endpoint. - AUTO_VALID: Packet Auto-Valid Disable
Value Name Description 0 - no effect. 1 - disable this bit to not automatically validate the current packet. - INTDIS_DMA: Interrupts Disable DMA
Value Name Description 0 - no effect. 1 - disable the "Interrupts Disable DMA". - NYET_DIS: NYET Enable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - no effect. 1 - let the hardware handle the handshake response for the High Speed Bulk OUT transfer. - DATAX_RX: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - disable DATAx Interrupt. - MDATA_RX: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - disable MDATA Interrupt. - ERR_OVFLW: Overflow Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Overflow Error Interrupt. - RX_BK_RDY: Received OUT Data Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Received OUT Data Interrupt. - TX_COMPLT: Transmitted IN Data Complete Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Transmitted IN Data Complete Interrupt. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable TX Packet Ready/Transaction Error Interrupt. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable TX Packet Ready/Transaction Error Interrupt. - RX_SETUP: Received SETUP/Error Flow Interrupt Disable
Value Name Description 0 - no effect. 1 - disable RX_SETUP/Error Flow ISO Interrupt. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Disable
Value Name Description 0 - no effect. 1 - disable RX_SETUP/Error Flow ISO Interrupt. - STALL_SNT: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_CRISO: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - NAK_IN: NAKIN/bank flush error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKIN/ Bank Flush Error Interrupt. - ERR_FLUSH: NAKIN/bank flush error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKIN/ Bank Flush Error Interrupt. - NAK_OUT: NAKOUT Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKOUT Interrupt. - BUSY_BANK: Busy Bank Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Busy Bank Interrupt. - SHRT_PCKT: Short Packet Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Short Packet Interrupt.
UDPHS UDPHS Endpoint Control Register (endpoint = 3)
Name: UDPHS_EPTCTL3
Access: read-only
Address: 0x400A416C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_ENABL |
- EPT_ENABL: Endpoint Enable
Value Name Description 0 - If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration. 1 - If set, the endpoint is enabled according to the device configuration. - AUTO_VALID: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
- INTDIS_DMA: Interrupt Disables DMA
- NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - If clear, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer. 1 - If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. - DATAX_RX: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received. - MDATA_RX: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data pay-load has been received. - ERR_OVFLW: Overflow Error Interrupt Enabled
Value Name Description 0 - Overflow Error Interrupt is masked. 1 - Overflow Error Interrupt is enabled. - RX_BK_RDY: Received OUT Data Interrupt Enabled
Value Name Description 0 - Received OUT Data Interrupt is masked. 1 - Received OUT Data Interrupt is enabled. - TX_COMPLT: Transmitted IN Data Complete Interrupt Enabled
Value Name Description 0 - Transmitted IN Data Complete Interrupt is masked. 1 - Transmitted IN Data Complete Interrupt is enabled. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Enabled
Value Name Description 0 - TX Packet Ready/Transaction Error Interrupt is masked. 1 - TX Packet Ready/Transaction Error Interrupt is enabled. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enabled
Value Name Description 0 - TX Packet Ready/Transaction Error Interrupt is masked. 1 - TX Packet Ready/Transaction Error Interrupt is enabled. - RX_SETUP: Received SETUP/Error Flow Interrupt Enabled
Value Name Description 0 - Received SETUP/Error Flow Interrupt is masked. 1 - Received SETUP/Error Flow Interrupt is enabled. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enabled
Value Name Description 0 - Received SETUP/Error Flow Interrupt is masked. 1 - Received SETUP/Error Flow Interrupt is enabled. - STALL_SNT: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - ERR_CRISO: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - NAK_IN: NAKIN/Bank Flush Error Interrupt Enabled
Value Name Description 0 - NAKIN Interrupt is masked. 1 - NAKIN/Bank Flush Error Interrupt is enabled. - ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enabled
Value Name Description 0 - NAKIN Interrupt is masked. 1 - NAKIN/Bank Flush Error Interrupt is enabled. - NAK_OUT: NAKOUT Interrupt Enabled
Value Name Description 0 - NAKOUT Interrupt is masked. 1 - NAKOUT Interrupt is enabled. - BUSY_BANK: Busy Bank Interrupt Enabled
Value Name Description 0 - BUSY_BANK Interrupt is masked. 1 - BUSY_BANK Interrupt is enabled. - SHRT_PCKT: Short Packet Interrupt Enabled
Value Name Description 0 - Short Packet Interrupt is masked. 1 - Short Packet Interrupt is enabled.
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UDPHS UDPHS Endpoint Set Status Register (endpoint = 3)
Name: UDPHS_EPTSETSTA3
Access: write-only
Address: 0x400A4174
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | TX_PK_RDY | - | KILL_BANK | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request Set
Value Name Description 0 - no effect. 1 - set this bit to request a STALL answer to the host for the next handshake - KILL_BANK: KILL Bank Set (for IN Endpoint)
Value Name Description 0 - no effect. 1 - kill the last written bank. - TX_PK_RDY: TX Packet Ready Set
Value Name Description 0 - no effect. 1 - set this bit after a packet has been written into the endpoint FIFO for IN data transfers
UDPHS UDPHS Endpoint Clear Status Register (endpoint = 3)
Name: UDPHS_EPTCLRSTA3
Access: write-only
Address: 0x400A4178
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | - | TX_COMPLT | RX_BK_RDY | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | TOGGLESQ | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request Clear
Value Name Description 0 - no effect. 1 - clear the STALL request. The next packets from host will not be STALLed. - TOGGLESQ: Data Toggle Clear
Value Name Description 0 - no effect. 1 - clear the PID data of the current bank - RX_BK_RDY: Received OUT Data Clear
Value Name Description 0 - no effect. 1 - clear the RX_BK_RDY flag of UDPHS_EPTSTAx. - TX_COMPLT: Transmitted IN Data Complete Clear
Value Name Description 0 - no effect. 1 - clear the TX_COMPLT flag of UDPHS_EPTSTAx. - RX_SETUP: Received SETUP/Error Flow Clear
Value Name Description 0 - no effect. 1 - clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx. - ERR_FL_ISO: Received SETUP/Error Flow Clear
Value Name Description 0 - no effect. 1 - clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx. - STALL_SNT: Stall Sent/Number of Transaction Error Clear
Value Name Description 0 - no effect. 1 - clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx. - ERR_NBTRA: Stall Sent/Number of Transaction Error Clear
Value Name Description 0 - no effect. 1 - clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx. - NAK_IN: NAKIN/Bank Flush Error Clear
Value Name Description 0 - no effect. 1 - clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. - ERR_FLUSH: NAKIN/Bank Flush Error Clear
Value Name Description 0 - no effect. 1 - clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. - NAK_OUT: NAKOUT Clear
Value Name Description 0 - no effect. 1 - clear the NAK_OUT flag of UDPHS_EPTSTAx.
UDPHS UDPHS Endpoint Status Register (endpoint = 3)
Name: UDPHS_EPTSTA3
Access: read-only
Address: 0x400A417C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | BYTE_COUNT | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BYTE_COUNT | BUSY_BANK_STA | CURRENT_BANK | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOGGLESQ_STA | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request
Value Name Description 0 - no effect. 1 - If set a STALL answer will be done to the host for the next handshake. - TOGGLESQ_STA: Toggle Sequencing
Value Name Description 0x0 DATA0 DATA0 0x1 DATA1 DATA1 0x2 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x3 MDATA MData (only for High Bandwidth Isochronous Endpoint) - ERR_OVFLW: Overflow Error
- RX_BK_RDY: Received OUT Data/KILL Bank
- KILL_BANK: Received OUT Data/KILL Bank
- TX_COMPLT: Transmitted IN Data Complete
- TX_PK_RDY: TX Packet Ready/Transaction Error
- ERR_TRANS: TX Packet Ready/Transaction Error
- RX_SETUP: Received SETUP/Error Flow
- ERR_FL_ISO: Received SETUP/Error Flow
- STALL_SNT: Stall Sent/CRC ISO Error/Number of Transaction Error
- ERR_CRISO: Stall Sent/CRC ISO Error/Number of Transaction Error
- ERR_NBTRA: Stall Sent/CRC ISO Error/Number of Transaction Error
- NAK_IN: NAK IN/Bank Flush Error
- ERR_FLUSH: NAK IN/Bank Flush Error
- NAK_OUT: NAK OUT
- CURRENT_BANK: Current Bank/Control Direction
- CONTROL_DIR: Current Bank/Control Direction
- BUSY_BANK_STA: Busy Bank Number
Value Name Description 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks - BYTE_COUNT: UDPHS Byte Count
- SHRT_PCKT: Short Packet
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UDPHS UDPHS Endpoint Configuration Register (endpoint = 4)
Name: UDPHS_EPTCFG4
Access: read-write
Address: 0x400A4180
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
EPT_MAPD | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | NB_TRANS | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BK_NUMBER | EPT_TYPE | EPT_DIR | EPT_SIZE |
- EPT_SIZE: Endpoint Size
Value Name Description 0x0 8 8 bytes 0x1 16 16 bytes 0x2 32 32 bytes 0x3 64 64 bytes 0x4 128 128 bytes 0x5 256 256 bytes 0x6 512 512 bytes 0x7 1024 1024 bytes - EPT_DIR: Endpoint Direction
Value Name Description 0 - Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. 1 - set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. - EPT_TYPE: Endpoint Type
Value Name Description 0x0 CTRL8 Control endpoint 0x1 ISO Isochronous endpoint 0x2 BULK Bulk endpoint 0x3 INT Interrupt endpoint - BK_NUMBER: Number of Banks
Value Name Description 0x0 0 Zero bank, the endpoint is not mapped in memory 0x1 1 One bank (bank 0) 0x2 2 Double bank (Ping-Pong: bank0/bank1) 0x3 3 Triple bank (bank0/bank1/bank2) - NB_TRANS: Number Of Transaction per Microframe
- EPT_MAPD: Endpoint Mapped
Value Name Description 0 - the user should reprogram the register with correct values. 1 - set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding:
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UDPHS UDPHS Endpoint Control Enable Register (endpoint = 4)
Name: UDPHS_EPTCTLENB4
Access: write-only
Address: 0x400A4184
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_ENABL |
- EPT_ENABL: Endpoint Enable
Value Name Description 0 - no effect. 1 - enable endpoint according to the device configuration. - AUTO_VALID: Packet Auto-Valid Enable
Value Name Description 0 - no effect. 1 - enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers. - INTDIS_DMA: Interrupts Disable DMA
Value Name Description 0 - no effect. 1 - If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled. - NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - no effect. 1 - forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. - DATAX_RX: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - enable DATAx Interrupt. - MDATA_RX: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - enable MDATA Interrupt. - ERR_OVFLW: Overflow Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Overflow Error Interrupt. - RX_BK_RDY: Received OUT Data Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Received OUT Data Interrupt. - TX_COMPLT: Transmitted IN Data Complete Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Transmitted IN Data Complete Interrupt. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable TX Packet Ready/Transaction Error Interrupt. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable TX Packet Ready/Transaction Error Interrupt. - RX_SETUP: Received SETUP/Error Flow Interrupt Enable
Value Name Description 0 - no effect. 1 - enable RX_SETUP/Error Flow ISO Interrupt. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enable
Value Name Description 0 - no effect. 1 - enable RX_SETUP/Error Flow ISO Interrupt. - STALL_SNT: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_CRISO: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_NBTRA: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - NAK_IN: NAKIN/Bank Flush Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKIN/Bank Flush Error Interrupt. - ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKIN/Bank Flush Error Interrupt. - NAK_OUT: NAKOUT Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKOUT Interrupt. - BUSY_BANK: Busy Bank Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Busy Bank Interrupt. - SHRT_PCKT: Short Packet Send/Short Packet Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Short Packet Interrupt.
UDPHS UDPHS Endpoint Control Disable Register (endpoint = 4)
Name: UDPHS_EPTCTLDIS4
Access: write-only
Address: 0x400A4188
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_DISABL |
- EPT_DISABL: Endpoint Disable
Value Name Description 0 - no effect. 1 - disable endpoint. - AUTO_VALID: Packet Auto-Valid Disable
Value Name Description 0 - no effect. 1 - disable this bit to not automatically validate the current packet. - INTDIS_DMA: Interrupts Disable DMA
Value Name Description 0 - no effect. 1 - disable the "Interrupts Disable DMA". - NYET_DIS: NYET Enable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - no effect. 1 - let the hardware handle the handshake response for the High Speed Bulk OUT transfer. - DATAX_RX: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - disable DATAx Interrupt. - MDATA_RX: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - disable MDATA Interrupt. - ERR_OVFLW: Overflow Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Overflow Error Interrupt. - RX_BK_RDY: Received OUT Data Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Received OUT Data Interrupt. - TX_COMPLT: Transmitted IN Data Complete Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Transmitted IN Data Complete Interrupt. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable TX Packet Ready/Transaction Error Interrupt. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable TX Packet Ready/Transaction Error Interrupt. - RX_SETUP: Received SETUP/Error Flow Interrupt Disable
Value Name Description 0 - no effect. 1 - disable RX_SETUP/Error Flow ISO Interrupt. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Disable
Value Name Description 0 - no effect. 1 - disable RX_SETUP/Error Flow ISO Interrupt. - STALL_SNT: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_CRISO: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - NAK_IN: NAKIN/bank flush error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKIN/ Bank Flush Error Interrupt. - ERR_FLUSH: NAKIN/bank flush error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKIN/ Bank Flush Error Interrupt. - NAK_OUT: NAKOUT Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKOUT Interrupt. - BUSY_BANK: Busy Bank Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Busy Bank Interrupt. - SHRT_PCKT: Short Packet Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Short Packet Interrupt.
UDPHS UDPHS Endpoint Control Register (endpoint = 4)
Name: UDPHS_EPTCTL4
Access: read-only
Address: 0x400A418C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_ENABL |
- EPT_ENABL: Endpoint Enable
Value Name Description 0 - If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration. 1 - If set, the endpoint is enabled according to the device configuration. - AUTO_VALID: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
- INTDIS_DMA: Interrupt Disables DMA
- NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - If clear, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer. 1 - If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. - DATAX_RX: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received. - MDATA_RX: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data pay-load has been received. - ERR_OVFLW: Overflow Error Interrupt Enabled
Value Name Description 0 - Overflow Error Interrupt is masked. 1 - Overflow Error Interrupt is enabled. - RX_BK_RDY: Received OUT Data Interrupt Enabled
Value Name Description 0 - Received OUT Data Interrupt is masked. 1 - Received OUT Data Interrupt is enabled. - TX_COMPLT: Transmitted IN Data Complete Interrupt Enabled
Value Name Description 0 - Transmitted IN Data Complete Interrupt is masked. 1 - Transmitted IN Data Complete Interrupt is enabled. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Enabled
Value Name Description 0 - TX Packet Ready/Transaction Error Interrupt is masked. 1 - TX Packet Ready/Transaction Error Interrupt is enabled. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enabled
Value Name Description 0 - TX Packet Ready/Transaction Error Interrupt is masked. 1 - TX Packet Ready/Transaction Error Interrupt is enabled. - RX_SETUP: Received SETUP/Error Flow Interrupt Enabled
Value Name Description 0 - Received SETUP/Error Flow Interrupt is masked. 1 - Received SETUP/Error Flow Interrupt is enabled. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enabled
Value Name Description 0 - Received SETUP/Error Flow Interrupt is masked. 1 - Received SETUP/Error Flow Interrupt is enabled. - STALL_SNT: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - ERR_CRISO: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - NAK_IN: NAKIN/Bank Flush Error Interrupt Enabled
Value Name Description 0 - NAKIN Interrupt is masked. 1 - NAKIN/Bank Flush Error Interrupt is enabled. - ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enabled
Value Name Description 0 - NAKIN Interrupt is masked. 1 - NAKIN/Bank Flush Error Interrupt is enabled. - NAK_OUT: NAKOUT Interrupt Enabled
Value Name Description 0 - NAKOUT Interrupt is masked. 1 - NAKOUT Interrupt is enabled. - BUSY_BANK: Busy Bank Interrupt Enabled
Value Name Description 0 - BUSY_BANK Interrupt is masked. 1 - BUSY_BANK Interrupt is enabled. - SHRT_PCKT: Short Packet Interrupt Enabled
Value Name Description 0 - Short Packet Interrupt is masked. 1 - Short Packet Interrupt is enabled.
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UDPHS UDPHS Endpoint Set Status Register (endpoint = 4)
Name: UDPHS_EPTSETSTA4
Access: write-only
Address: 0x400A4194
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | TX_PK_RDY | - | KILL_BANK | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request Set
Value Name Description 0 - no effect. 1 - set this bit to request a STALL answer to the host for the next handshake - KILL_BANK: KILL Bank Set (for IN Endpoint)
Value Name Description 0 - no effect. 1 - kill the last written bank. - TX_PK_RDY: TX Packet Ready Set
Value Name Description 0 - no effect. 1 - set this bit after a packet has been written into the endpoint FIFO for IN data transfers
UDPHS UDPHS Endpoint Clear Status Register (endpoint = 4)
Name: UDPHS_EPTCLRSTA4
Access: write-only
Address: 0x400A4198
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | - | TX_COMPLT | RX_BK_RDY | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | TOGGLESQ | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request Clear
Value Name Description 0 - no effect. 1 - clear the STALL request. The next packets from host will not be STALLed. - TOGGLESQ: Data Toggle Clear
Value Name Description 0 - no effect. 1 - clear the PID data of the current bank - RX_BK_RDY: Received OUT Data Clear
Value Name Description 0 - no effect. 1 - clear the RX_BK_RDY flag of UDPHS_EPTSTAx. - TX_COMPLT: Transmitted IN Data Complete Clear
Value Name Description 0 - no effect. 1 - clear the TX_COMPLT flag of UDPHS_EPTSTAx. - RX_SETUP: Received SETUP/Error Flow Clear
Value Name Description 0 - no effect. 1 - clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx. - ERR_FL_ISO: Received SETUP/Error Flow Clear
Value Name Description 0 - no effect. 1 - clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx. - STALL_SNT: Stall Sent/Number of Transaction Error Clear
Value Name Description 0 - no effect. 1 - clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx. - ERR_NBTRA: Stall Sent/Number of Transaction Error Clear
Value Name Description 0 - no effect. 1 - clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx. - NAK_IN: NAKIN/Bank Flush Error Clear
Value Name Description 0 - no effect. 1 - clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. - ERR_FLUSH: NAKIN/Bank Flush Error Clear
Value Name Description 0 - no effect. 1 - clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. - NAK_OUT: NAKOUT Clear
Value Name Description 0 - no effect. 1 - clear the NAK_OUT flag of UDPHS_EPTSTAx.
UDPHS UDPHS Endpoint Status Register (endpoint = 4)
Name: UDPHS_EPTSTA4
Access: read-only
Address: 0x400A419C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | BYTE_COUNT | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BYTE_COUNT | BUSY_BANK_STA | CURRENT_BANK | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOGGLESQ_STA | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request
Value Name Description 0 - no effect. 1 - If set a STALL answer will be done to the host for the next handshake. - TOGGLESQ_STA: Toggle Sequencing
Value Name Description 0x0 DATA0 DATA0 0x1 DATA1 DATA1 0x2 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x3 MDATA MData (only for High Bandwidth Isochronous Endpoint) - ERR_OVFLW: Overflow Error
- RX_BK_RDY: Received OUT Data/KILL Bank
- KILL_BANK: Received OUT Data/KILL Bank
- TX_COMPLT: Transmitted IN Data Complete
- TX_PK_RDY: TX Packet Ready/Transaction Error
- ERR_TRANS: TX Packet Ready/Transaction Error
- RX_SETUP: Received SETUP/Error Flow
- ERR_FL_ISO: Received SETUP/Error Flow
- STALL_SNT: Stall Sent/CRC ISO Error/Number of Transaction Error
- ERR_CRISO: Stall Sent/CRC ISO Error/Number of Transaction Error
- ERR_NBTRA: Stall Sent/CRC ISO Error/Number of Transaction Error
- NAK_IN: NAK IN/Bank Flush Error
- ERR_FLUSH: NAK IN/Bank Flush Error
- NAK_OUT: NAK OUT
- CURRENT_BANK: Current Bank/Control Direction
- CONTROL_DIR: Current Bank/Control Direction
- BUSY_BANK_STA: Busy Bank Number
Value Name Description 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks - BYTE_COUNT: UDPHS Byte Count
- SHRT_PCKT: Short Packet
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UDPHS UDPHS Endpoint Configuration Register (endpoint = 5)
Name: UDPHS_EPTCFG5
Access: read-write
Address: 0x400A41A0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
EPT_MAPD | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | NB_TRANS | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BK_NUMBER | EPT_TYPE | EPT_DIR | EPT_SIZE |
- EPT_SIZE: Endpoint Size
Value Name Description 0x0 8 8 bytes 0x1 16 16 bytes 0x2 32 32 bytes 0x3 64 64 bytes 0x4 128 128 bytes 0x5 256 256 bytes 0x6 512 512 bytes 0x7 1024 1024 bytes - EPT_DIR: Endpoint Direction
Value Name Description 0 - Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. 1 - set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. - EPT_TYPE: Endpoint Type
Value Name Description 0x0 CTRL8 Control endpoint 0x1 ISO Isochronous endpoint 0x2 BULK Bulk endpoint 0x3 INT Interrupt endpoint - BK_NUMBER: Number of Banks
Value Name Description 0x0 0 Zero bank, the endpoint is not mapped in memory 0x1 1 One bank (bank 0) 0x2 2 Double bank (Ping-Pong: bank0/bank1) 0x3 3 Triple bank (bank0/bank1/bank2) - NB_TRANS: Number Of Transaction per Microframe
- EPT_MAPD: Endpoint Mapped
Value Name Description 0 - the user should reprogram the register with correct values. 1 - set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding:
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UDPHS UDPHS Endpoint Control Enable Register (endpoint = 5)
Name: UDPHS_EPTCTLENB5
Access: write-only
Address: 0x400A41A4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_ENABL |
- EPT_ENABL: Endpoint Enable
Value Name Description 0 - no effect. 1 - enable endpoint according to the device configuration. - AUTO_VALID: Packet Auto-Valid Enable
Value Name Description 0 - no effect. 1 - enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers. - INTDIS_DMA: Interrupts Disable DMA
Value Name Description 0 - no effect. 1 - If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled. - NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - no effect. 1 - forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. - DATAX_RX: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - enable DATAx Interrupt. - MDATA_RX: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - enable MDATA Interrupt. - ERR_OVFLW: Overflow Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Overflow Error Interrupt. - RX_BK_RDY: Received OUT Data Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Received OUT Data Interrupt. - TX_COMPLT: Transmitted IN Data Complete Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Transmitted IN Data Complete Interrupt. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable TX Packet Ready/Transaction Error Interrupt. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable TX Packet Ready/Transaction Error Interrupt. - RX_SETUP: Received SETUP/Error Flow Interrupt Enable
Value Name Description 0 - no effect. 1 - enable RX_SETUP/Error Flow ISO Interrupt. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enable
Value Name Description 0 - no effect. 1 - enable RX_SETUP/Error Flow ISO Interrupt. - STALL_SNT: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_CRISO: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_NBTRA: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - NAK_IN: NAKIN/Bank Flush Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKIN/Bank Flush Error Interrupt. - ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKIN/Bank Flush Error Interrupt. - NAK_OUT: NAKOUT Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKOUT Interrupt. - BUSY_BANK: Busy Bank Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Busy Bank Interrupt. - SHRT_PCKT: Short Packet Send/Short Packet Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Short Packet Interrupt.
UDPHS UDPHS Endpoint Control Disable Register (endpoint = 5)
Name: UDPHS_EPTCTLDIS5
Access: write-only
Address: 0x400A41A8
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_DISABL |
- EPT_DISABL: Endpoint Disable
Value Name Description 0 - no effect. 1 - disable endpoint. - AUTO_VALID: Packet Auto-Valid Disable
Value Name Description 0 - no effect. 1 - disable this bit to not automatically validate the current packet. - INTDIS_DMA: Interrupts Disable DMA
Value Name Description 0 - no effect. 1 - disable the "Interrupts Disable DMA". - NYET_DIS: NYET Enable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - no effect. 1 - let the hardware handle the handshake response for the High Speed Bulk OUT transfer. - DATAX_RX: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - disable DATAx Interrupt. - MDATA_RX: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - disable MDATA Interrupt. - ERR_OVFLW: Overflow Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Overflow Error Interrupt. - RX_BK_RDY: Received OUT Data Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Received OUT Data Interrupt. - TX_COMPLT: Transmitted IN Data Complete Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Transmitted IN Data Complete Interrupt. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable TX Packet Ready/Transaction Error Interrupt. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable TX Packet Ready/Transaction Error Interrupt. - RX_SETUP: Received SETUP/Error Flow Interrupt Disable
Value Name Description 0 - no effect. 1 - disable RX_SETUP/Error Flow ISO Interrupt. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Disable
Value Name Description 0 - no effect. 1 - disable RX_SETUP/Error Flow ISO Interrupt. - STALL_SNT: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_CRISO: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - NAK_IN: NAKIN/bank flush error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKIN/ Bank Flush Error Interrupt. - ERR_FLUSH: NAKIN/bank flush error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKIN/ Bank Flush Error Interrupt. - NAK_OUT: NAKOUT Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKOUT Interrupt. - BUSY_BANK: Busy Bank Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Busy Bank Interrupt. - SHRT_PCKT: Short Packet Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Short Packet Interrupt.
UDPHS UDPHS Endpoint Control Register (endpoint = 5)
Name: UDPHS_EPTCTL5
Access: read-only
Address: 0x400A41AC
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_ENABL |
- EPT_ENABL: Endpoint Enable
Value Name Description 0 - If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration. 1 - If set, the endpoint is enabled according to the device configuration. - AUTO_VALID: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
- INTDIS_DMA: Interrupt Disables DMA
- NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - If clear, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer. 1 - If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. - DATAX_RX: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received. - MDATA_RX: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data pay-load has been received. - ERR_OVFLW: Overflow Error Interrupt Enabled
Value Name Description 0 - Overflow Error Interrupt is masked. 1 - Overflow Error Interrupt is enabled. - RX_BK_RDY: Received OUT Data Interrupt Enabled
Value Name Description 0 - Received OUT Data Interrupt is masked. 1 - Received OUT Data Interrupt is enabled. - TX_COMPLT: Transmitted IN Data Complete Interrupt Enabled
Value Name Description 0 - Transmitted IN Data Complete Interrupt is masked. 1 - Transmitted IN Data Complete Interrupt is enabled. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Enabled
Value Name Description 0 - TX Packet Ready/Transaction Error Interrupt is masked. 1 - TX Packet Ready/Transaction Error Interrupt is enabled. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enabled
Value Name Description 0 - TX Packet Ready/Transaction Error Interrupt is masked. 1 - TX Packet Ready/Transaction Error Interrupt is enabled. - RX_SETUP: Received SETUP/Error Flow Interrupt Enabled
Value Name Description 0 - Received SETUP/Error Flow Interrupt is masked. 1 - Received SETUP/Error Flow Interrupt is enabled. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enabled
Value Name Description 0 - Received SETUP/Error Flow Interrupt is masked. 1 - Received SETUP/Error Flow Interrupt is enabled. - STALL_SNT: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - ERR_CRISO: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - NAK_IN: NAKIN/Bank Flush Error Interrupt Enabled
Value Name Description 0 - NAKIN Interrupt is masked. 1 - NAKIN/Bank Flush Error Interrupt is enabled. - ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enabled
Value Name Description 0 - NAKIN Interrupt is masked. 1 - NAKIN/Bank Flush Error Interrupt is enabled. - NAK_OUT: NAKOUT Interrupt Enabled
Value Name Description 0 - NAKOUT Interrupt is masked. 1 - NAKOUT Interrupt is enabled. - BUSY_BANK: Busy Bank Interrupt Enabled
Value Name Description 0 - BUSY_BANK Interrupt is masked. 1 - BUSY_BANK Interrupt is enabled. - SHRT_PCKT: Short Packet Interrupt Enabled
Value Name Description 0 - Short Packet Interrupt is masked. 1 - Short Packet Interrupt is enabled.
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UDPHS UDPHS Endpoint Set Status Register (endpoint = 5)
Name: UDPHS_EPTSETSTA5
Access: write-only
Address: 0x400A41B4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | TX_PK_RDY | - | KILL_BANK | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request Set
Value Name Description 0 - no effect. 1 - set this bit to request a STALL answer to the host for the next handshake - KILL_BANK: KILL Bank Set (for IN Endpoint)
Value Name Description 0 - no effect. 1 - kill the last written bank. - TX_PK_RDY: TX Packet Ready Set
Value Name Description 0 - no effect. 1 - set this bit after a packet has been written into the endpoint FIFO for IN data transfers
UDPHS UDPHS Endpoint Clear Status Register (endpoint = 5)
Name: UDPHS_EPTCLRSTA5
Access: write-only
Address: 0x400A41B8
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | - | TX_COMPLT | RX_BK_RDY | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | TOGGLESQ | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request Clear
Value Name Description 0 - no effect. 1 - clear the STALL request. The next packets from host will not be STALLed. - TOGGLESQ: Data Toggle Clear
Value Name Description 0 - no effect. 1 - clear the PID data of the current bank - RX_BK_RDY: Received OUT Data Clear
Value Name Description 0 - no effect. 1 - clear the RX_BK_RDY flag of UDPHS_EPTSTAx. - TX_COMPLT: Transmitted IN Data Complete Clear
Value Name Description 0 - no effect. 1 - clear the TX_COMPLT flag of UDPHS_EPTSTAx. - RX_SETUP: Received SETUP/Error Flow Clear
Value Name Description 0 - no effect. 1 - clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx. - ERR_FL_ISO: Received SETUP/Error Flow Clear
Value Name Description 0 - no effect. 1 - clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx. - STALL_SNT: Stall Sent/Number of Transaction Error Clear
Value Name Description 0 - no effect. 1 - clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx. - ERR_NBTRA: Stall Sent/Number of Transaction Error Clear
Value Name Description 0 - no effect. 1 - clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx. - NAK_IN: NAKIN/Bank Flush Error Clear
Value Name Description 0 - no effect. 1 - clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. - ERR_FLUSH: NAKIN/Bank Flush Error Clear
Value Name Description 0 - no effect. 1 - clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. - NAK_OUT: NAKOUT Clear
Value Name Description 0 - no effect. 1 - clear the NAK_OUT flag of UDPHS_EPTSTAx.
UDPHS UDPHS Endpoint Status Register (endpoint = 5)
Name: UDPHS_EPTSTA5
Access: read-only
Address: 0x400A41BC
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | BYTE_COUNT | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BYTE_COUNT | BUSY_BANK_STA | CURRENT_BANK | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOGGLESQ_STA | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request
Value Name Description 0 - no effect. 1 - If set a STALL answer will be done to the host for the next handshake. - TOGGLESQ_STA: Toggle Sequencing
Value Name Description 0x0 DATA0 DATA0 0x1 DATA1 DATA1 0x2 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x3 MDATA MData (only for High Bandwidth Isochronous Endpoint) - ERR_OVFLW: Overflow Error
- RX_BK_RDY: Received OUT Data/KILL Bank
- KILL_BANK: Received OUT Data/KILL Bank
- TX_COMPLT: Transmitted IN Data Complete
- TX_PK_RDY: TX Packet Ready/Transaction Error
- ERR_TRANS: TX Packet Ready/Transaction Error
- RX_SETUP: Received SETUP/Error Flow
- ERR_FL_ISO: Received SETUP/Error Flow
- STALL_SNT: Stall Sent/CRC ISO Error/Number of Transaction Error
- ERR_CRISO: Stall Sent/CRC ISO Error/Number of Transaction Error
- ERR_NBTRA: Stall Sent/CRC ISO Error/Number of Transaction Error
- NAK_IN: NAK IN/Bank Flush Error
- ERR_FLUSH: NAK IN/Bank Flush Error
- NAK_OUT: NAK OUT
- CURRENT_BANK: Current Bank/Control Direction
- CONTROL_DIR: Current Bank/Control Direction
- BUSY_BANK_STA: Busy Bank Number
Value Name Description 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks - BYTE_COUNT: UDPHS Byte Count
- SHRT_PCKT: Short Packet
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-
-
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UDPHS UDPHS Endpoint Configuration Register (endpoint = 6)
Name: UDPHS_EPTCFG6
Access: read-write
Address: 0x400A41C0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
EPT_MAPD | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | NB_TRANS | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BK_NUMBER | EPT_TYPE | EPT_DIR | EPT_SIZE |
- EPT_SIZE: Endpoint Size
Value Name Description 0x0 8 8 bytes 0x1 16 16 bytes 0x2 32 32 bytes 0x3 64 64 bytes 0x4 128 128 bytes 0x5 256 256 bytes 0x6 512 512 bytes 0x7 1024 1024 bytes - EPT_DIR: Endpoint Direction
Value Name Description 0 - Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. 1 - set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. - EPT_TYPE: Endpoint Type
Value Name Description 0x0 CTRL8 Control endpoint 0x1 ISO Isochronous endpoint 0x2 BULK Bulk endpoint 0x3 INT Interrupt endpoint - BK_NUMBER: Number of Banks
Value Name Description 0x0 0 Zero bank, the endpoint is not mapped in memory 0x1 1 One bank (bank 0) 0x2 2 Double bank (Ping-Pong: bank0/bank1) 0x3 3 Triple bank (bank0/bank1/bank2) - NB_TRANS: Number Of Transaction per Microframe
- EPT_MAPD: Endpoint Mapped
Value Name Description 0 - the user should reprogram the register with correct values. 1 - set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding:
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UDPHS UDPHS Endpoint Control Enable Register (endpoint = 6)
Name: UDPHS_EPTCTLENB6
Access: write-only
Address: 0x400A41C4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_ENABL |
- EPT_ENABL: Endpoint Enable
Value Name Description 0 - no effect. 1 - enable endpoint according to the device configuration. - AUTO_VALID: Packet Auto-Valid Enable
Value Name Description 0 - no effect. 1 - enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers. - INTDIS_DMA: Interrupts Disable DMA
Value Name Description 0 - no effect. 1 - If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled. - NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - no effect. 1 - forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. - DATAX_RX: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - enable DATAx Interrupt. - MDATA_RX: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - enable MDATA Interrupt. - ERR_OVFLW: Overflow Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Overflow Error Interrupt. - RX_BK_RDY: Received OUT Data Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Received OUT Data Interrupt. - TX_COMPLT: Transmitted IN Data Complete Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Transmitted IN Data Complete Interrupt. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable TX Packet Ready/Transaction Error Interrupt. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable TX Packet Ready/Transaction Error Interrupt. - RX_SETUP: Received SETUP/Error Flow Interrupt Enable
Value Name Description 0 - no effect. 1 - enable RX_SETUP/Error Flow ISO Interrupt. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enable
Value Name Description 0 - no effect. 1 - enable RX_SETUP/Error Flow ISO Interrupt. - STALL_SNT: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_CRISO: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_NBTRA: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - NAK_IN: NAKIN/Bank Flush Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKIN/Bank Flush Error Interrupt. - ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKIN/Bank Flush Error Interrupt. - NAK_OUT: NAKOUT Interrupt Enable
Value Name Description 0 - no effect. 1 - enable NAKOUT Interrupt. - BUSY_BANK: Busy Bank Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Busy Bank Interrupt. - SHRT_PCKT: Short Packet Send/Short Packet Interrupt Enable
Value Name Description 0 - no effect. 1 - enable Short Packet Interrupt.
UDPHS UDPHS Endpoint Control Disable Register (endpoint = 6)
Name: UDPHS_EPTCTLDIS6
Access: write-only
Address: 0x400A41C8
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_DISABL |
- EPT_DISABL: Endpoint Disable
Value Name Description 0 - no effect. 1 - disable endpoint. - AUTO_VALID: Packet Auto-Valid Disable
Value Name Description 0 - no effect. 1 - disable this bit to not automatically validate the current packet. - INTDIS_DMA: Interrupts Disable DMA
Value Name Description 0 - no effect. 1 - disable the "Interrupts Disable DMA". - NYET_DIS: NYET Enable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - no effect. 1 - let the hardware handle the handshake response for the High Speed Bulk OUT transfer. - DATAX_RX: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - disable DATAx Interrupt. - MDATA_RX: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - disable MDATA Interrupt. - ERR_OVFLW: Overflow Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Overflow Error Interrupt. - RX_BK_RDY: Received OUT Data Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Received OUT Data Interrupt. - TX_COMPLT: Transmitted IN Data Complete Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Transmitted IN Data Complete Interrupt. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable TX Packet Ready/Transaction Error Interrupt. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable TX Packet Ready/Transaction Error Interrupt. - RX_SETUP: Received SETUP/Error Flow Interrupt Disable
Value Name Description 0 - no effect. 1 - disable RX_SETUP/Error Flow ISO Interrupt. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Disable
Value Name Description 0 - no effect. 1 - disable RX_SETUP/Error Flow ISO Interrupt. - STALL_SNT: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_CRISO: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. - NAK_IN: NAKIN/bank flush error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKIN/ Bank Flush Error Interrupt. - ERR_FLUSH: NAKIN/bank flush error Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKIN/ Bank Flush Error Interrupt. - NAK_OUT: NAKOUT Interrupt Disable
Value Name Description 0 - no effect. 1 - disable NAKOUT Interrupt. - BUSY_BANK: Busy Bank Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Busy Bank Interrupt. - SHRT_PCKT: Short Packet Interrupt Disable
Value Name Description 0 - no effect. 1 - disable Short Packet Interrupt.
UDPHS UDPHS Endpoint Control Register (endpoint = 6)
Name: UDPHS_EPTCTL6
Access: read-only
Address: 0x400A41CC
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | BUSY_BANK | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDATA_RX | DATAX_RX | - | NYET_DIS | INTDIS_DMA | - | AUTO_VALID | EPT_ENABL |
- EPT_ENABL: Endpoint Enable
Value Name Description 0 - If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration. 1 - If set, the endpoint is enabled according to the device configuration. - AUTO_VALID: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
- INTDIS_DMA: Interrupt Disables DMA
- NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
Value Name Description 0 - If clear, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer. 1 - If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. - DATAX_RX: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received. - MDATA_RX: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
Value Name Description 0 - no effect. 1 - send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data pay-load has been received. - ERR_OVFLW: Overflow Error Interrupt Enabled
Value Name Description 0 - Overflow Error Interrupt is masked. 1 - Overflow Error Interrupt is enabled. - RX_BK_RDY: Received OUT Data Interrupt Enabled
Value Name Description 0 - Received OUT Data Interrupt is masked. 1 - Received OUT Data Interrupt is enabled. - TX_COMPLT: Transmitted IN Data Complete Interrupt Enabled
Value Name Description 0 - Transmitted IN Data Complete Interrupt is masked. 1 - Transmitted IN Data Complete Interrupt is enabled. - TX_PK_RDY: TX Packet Ready/Transaction Error Interrupt Enabled
Value Name Description 0 - TX Packet Ready/Transaction Error Interrupt is masked. 1 - TX Packet Ready/Transaction Error Interrupt is enabled. - ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enabled
Value Name Description 0 - TX Packet Ready/Transaction Error Interrupt is masked. 1 - TX Packet Ready/Transaction Error Interrupt is enabled. - RX_SETUP: Received SETUP/Error Flow Interrupt Enabled
Value Name Description 0 - Received SETUP/Error Flow Interrupt is masked. 1 - Received SETUP/Error Flow Interrupt is enabled. - ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enabled
Value Name Description 0 - Received SETUP/Error Flow Interrupt is masked. 1 - Received SETUP/Error Flow Interrupt is enabled. - STALL_SNT: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - ERR_CRISO: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
Value Name Description 0 - Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 - Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. - NAK_IN: NAKIN/Bank Flush Error Interrupt Enabled
Value Name Description 0 - NAKIN Interrupt is masked. 1 - NAKIN/Bank Flush Error Interrupt is enabled. - ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enabled
Value Name Description 0 - NAKIN Interrupt is masked. 1 - NAKIN/Bank Flush Error Interrupt is enabled. - NAK_OUT: NAKOUT Interrupt Enabled
Value Name Description 0 - NAKOUT Interrupt is masked. 1 - NAKOUT Interrupt is enabled. - BUSY_BANK: Busy Bank Interrupt Enabled
Value Name Description 0 - BUSY_BANK Interrupt is masked. 1 - BUSY_BANK Interrupt is enabled. - SHRT_PCKT: Short Packet Interrupt Enabled
Value Name Description 0 - Short Packet Interrupt is masked. 1 - Short Packet Interrupt is enabled.
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UDPHS UDPHS Endpoint Set Status Register (endpoint = 6)
Name: UDPHS_EPTSETSTA6
Access: write-only
Address: 0x400A41D4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | TX_PK_RDY | - | KILL_BANK | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request Set
Value Name Description 0 - no effect. 1 - set this bit to request a STALL answer to the host for the next handshake - KILL_BANK: KILL Bank Set (for IN Endpoint)
Value Name Description 0 - no effect. 1 - kill the last written bank. - TX_PK_RDY: TX Packet Ready Set
Value Name Description 0 - no effect. 1 - set this bit after a packet has been written into the endpoint FIFO for IN data transfers
UDPHS UDPHS Endpoint Clear Status Register (endpoint = 6)
Name: UDPHS_EPTCLRSTA6
Access: write-only
Address: 0x400A41D8
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | - | TX_COMPLT | RX_BK_RDY | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | TOGGLESQ | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request Clear
Value Name Description 0 - no effect. 1 - clear the STALL request. The next packets from host will not be STALLed. - TOGGLESQ: Data Toggle Clear
Value Name Description 0 - no effect. 1 - clear the PID data of the current bank - RX_BK_RDY: Received OUT Data Clear
Value Name Description 0 - no effect. 1 - clear the RX_BK_RDY flag of UDPHS_EPTSTAx. - TX_COMPLT: Transmitted IN Data Complete Clear
Value Name Description 0 - no effect. 1 - clear the TX_COMPLT flag of UDPHS_EPTSTAx. - RX_SETUP: Received SETUP/Error Flow Clear
Value Name Description 0 - no effect. 1 - clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx. - ERR_FL_ISO: Received SETUP/Error Flow Clear
Value Name Description 0 - no effect. 1 - clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx. - STALL_SNT: Stall Sent/Number of Transaction Error Clear
Value Name Description 0 - no effect. 1 - clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx. - ERR_NBTRA: Stall Sent/Number of Transaction Error Clear
Value Name Description 0 - no effect. 1 - clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx. - NAK_IN: NAKIN/Bank Flush Error Clear
Value Name Description 0 - no effect. 1 - clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. - ERR_FLUSH: NAKIN/Bank Flush Error Clear
Value Name Description 0 - no effect. 1 - clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. - NAK_OUT: NAKOUT Clear
Value Name Description 0 - no effect. 1 - clear the NAK_OUT flag of UDPHS_EPTSTAx.
UDPHS UDPHS Endpoint Status Register (endpoint = 6)
Name: UDPHS_EPTSTA6
Access: read-only
Address: 0x400A41DC
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SHRT_PCKT | BYTE_COUNT | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BYTE_COUNT | BUSY_BANK_STA | CURRENT_BANK | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAK_OUT | NAK_IN | STALL_SNT | RX_SETUP | TX_PK_RDY | TX_COMPLT | RX_BK_RDY | ERR_OVFLW |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOGGLESQ_STA | FRCESTALL | - | - | - | - | - |
- FRCESTALL: Stall Handshake Request
Value Name Description 0 - no effect. 1 - If set a STALL answer will be done to the host for the next handshake. - TOGGLESQ_STA: Toggle Sequencing
Value Name Description 0x0 DATA0 DATA0 0x1 DATA1 DATA1 0x2 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x3 MDATA MData (only for High Bandwidth Isochronous Endpoint) - ERR_OVFLW: Overflow Error
- RX_BK_RDY: Received OUT Data/KILL Bank
- KILL_BANK: Received OUT Data/KILL Bank
- TX_COMPLT: Transmitted IN Data Complete
- TX_PK_RDY: TX Packet Ready/Transaction Error
- ERR_TRANS: TX Packet Ready/Transaction Error
- RX_SETUP: Received SETUP/Error Flow
- ERR_FL_ISO: Received SETUP/Error Flow
- STALL_SNT: Stall Sent/CRC ISO Error/Number of Transaction Error
- ERR_CRISO: Stall Sent/CRC ISO Error/Number of Transaction Error
- ERR_NBTRA: Stall Sent/CRC ISO Error/Number of Transaction Error
- NAK_IN: NAK IN/Bank Flush Error
- ERR_FLUSH: NAK IN/Bank Flush Error
- NAK_OUT: NAK OUT
- CURRENT_BANK: Current Bank/Control Direction
- CONTROL_DIR: Current Bank/Control Direction
- BUSY_BANK_STA: Busy Bank Number
Value Name Description 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks - BYTE_COUNT: UDPHS Byte Count
- SHRT_PCKT: Short Packet
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UDPHS UDPHS DMA Next Descriptor Address Register (channel = 0)
Name: UDPHS_DMANXTDSC0
Access: read-write
Address: 0x400A4300
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NXT_DSC_ADD | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NXT_DSC_ADD | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NXT_DSC_ADD | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NXT_DSC_ADD |
- NXT_DSC_ADD
-
UDPHS UDPHS DMA Channel Address Register (channel = 0)
Name: UDPHS_DMAADDRESS0
Access: read-write
Address: 0x400A4304
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_ADD | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_ADD | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BUFF_ADD | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUFF_ADD |
- BUFF_ADD
-
UDPHS UDPHS DMA Channel Control Register (channel = 0)
Name: UDPHS_DMACONTROL0
Access: read-write
Address: 0x400A4308
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_LENGTH | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_LENGTH | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB |
- CHANN_ENB
- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable (Command)
- END_TR_EN: End of Transfer Enable (Control)
Value Name Description 0 - USB end of transfer is ignored. 1 - UDPHS device can put an end to the current buffer transfer. - END_B_EN: End of Buffer Enable (Control)
Value Name Description 0 - DMA Buffer End has no impact on USB packet transfer. 1 - endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID and SHRT_PCKT fields) at DMA Buffer End, i.e. when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0. - END_TR_IT: End of Transfer Interrupt Enable
Value Name Description 0 - UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST rising. 1 - an interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer. - END_BUFFIT: End of Buffer Interrupt Enable
Value Name Description 0 - UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt. 1 - an interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero. - DESC_LD_IT: Descriptor Loaded Interrupt Enable
Value Name Description 0 - UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt. 1 - an interrupt is generated when a descriptor has been loaded from the bus. - BURST_LCK: Burst Lock Enable
Value Name Description 0 - the DMA never locks bus access. 1 - USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration. - BUFF_LENGTH: Buffer Byte Length (Write-only)
-
-
-
UDPHS UDPHS DMA Channel Status Register (channel = 0)
Name: UDPHS_DMASTATUS0
Access: read-write
Address: 0x400A430C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_COUNT | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_COUNT | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB |
- CHANN_ENB: Channel Enable Status
Value Name Description 0 - if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx register LDNXT_DSC bit is set. 1 - if set, the DMA channel is currently enabled and transfers data upon request. - CHANN_ACT: Channel Active Status
Value Name Description 0 - the DMA channel is no longer trying to source the packet data. 1 - the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel. - END_TR_ST: End of Channel Transfer Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer. - END_BF_ST: End of Channel Buffer Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when the BUFF_COUNT downcount reach zero. - DESC_LDST: Descriptor Loaded Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when a descriptor has been loaded from the system bus. - BUFF_COUNT: Buffer Byte Count
-
UDPHS UDPHS DMA Next Descriptor Address Register (channel = 1)
Name: UDPHS_DMANXTDSC1
Access: read-write
Address: 0x400A4310
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NXT_DSC_ADD | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NXT_DSC_ADD | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NXT_DSC_ADD | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NXT_DSC_ADD |
- NXT_DSC_ADD
-
UDPHS UDPHS DMA Channel Address Register (channel = 1)
Name: UDPHS_DMAADDRESS1
Access: read-write
Address: 0x400A4314
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_ADD | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_ADD | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BUFF_ADD | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUFF_ADD |
- BUFF_ADD
-
UDPHS UDPHS DMA Channel Control Register (channel = 1)
Name: UDPHS_DMACONTROL1
Access: read-write
Address: 0x400A4318
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_LENGTH | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_LENGTH | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB |
- CHANN_ENB
- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable (Command)
- END_TR_EN: End of Transfer Enable (Control)
Value Name Description 0 - USB end of transfer is ignored. 1 - UDPHS device can put an end to the current buffer transfer. - END_B_EN: End of Buffer Enable (Control)
Value Name Description 0 - DMA Buffer End has no impact on USB packet transfer. 1 - endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID and SHRT_PCKT fields) at DMA Buffer End, i.e. when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0. - END_TR_IT: End of Transfer Interrupt Enable
Value Name Description 0 - UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST rising. 1 - an interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer. - END_BUFFIT: End of Buffer Interrupt Enable
Value Name Description 0 - UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt. 1 - an interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero. - DESC_LD_IT: Descriptor Loaded Interrupt Enable
Value Name Description 0 - UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt. 1 - an interrupt is generated when a descriptor has been loaded from the bus. - BURST_LCK: Burst Lock Enable
Value Name Description 0 - the DMA never locks bus access. 1 - USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration. - BUFF_LENGTH: Buffer Byte Length (Write-only)
-
-
-
UDPHS UDPHS DMA Channel Status Register (channel = 1)
Name: UDPHS_DMASTATUS1
Access: read-write
Address: 0x400A431C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_COUNT | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_COUNT | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB |
- CHANN_ENB: Channel Enable Status
Value Name Description 0 - if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx register LDNXT_DSC bit is set. 1 - if set, the DMA channel is currently enabled and transfers data upon request. - CHANN_ACT: Channel Active Status
Value Name Description 0 - the DMA channel is no longer trying to source the packet data. 1 - the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel. - END_TR_ST: End of Channel Transfer Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer. - END_BF_ST: End of Channel Buffer Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when the BUFF_COUNT downcount reach zero. - DESC_LDST: Descriptor Loaded Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when a descriptor has been loaded from the system bus. - BUFF_COUNT: Buffer Byte Count
-
UDPHS UDPHS DMA Next Descriptor Address Register (channel = 2)
Name: UDPHS_DMANXTDSC2
Access: read-write
Address: 0x400A4320
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NXT_DSC_ADD | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NXT_DSC_ADD | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NXT_DSC_ADD | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NXT_DSC_ADD |
- NXT_DSC_ADD
-
UDPHS UDPHS DMA Channel Address Register (channel = 2)
Name: UDPHS_DMAADDRESS2
Access: read-write
Address: 0x400A4324
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_ADD | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_ADD | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BUFF_ADD | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUFF_ADD |
- BUFF_ADD
-
UDPHS UDPHS DMA Channel Control Register (channel = 2)
Name: UDPHS_DMACONTROL2
Access: read-write
Address: 0x400A4328
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_LENGTH | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_LENGTH | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB |
- CHANN_ENB
- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable (Command)
- END_TR_EN: End of Transfer Enable (Control)
Value Name Description 0 - USB end of transfer is ignored. 1 - UDPHS device can put an end to the current buffer transfer. - END_B_EN: End of Buffer Enable (Control)
Value Name Description 0 - DMA Buffer End has no impact on USB packet transfer. 1 - endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID and SHRT_PCKT fields) at DMA Buffer End, i.e. when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0. - END_TR_IT: End of Transfer Interrupt Enable
Value Name Description 0 - UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST rising. 1 - an interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer. - END_BUFFIT: End of Buffer Interrupt Enable
Value Name Description 0 - UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt. 1 - an interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero. - DESC_LD_IT: Descriptor Loaded Interrupt Enable
Value Name Description 0 - UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt. 1 - an interrupt is generated when a descriptor has been loaded from the bus. - BURST_LCK: Burst Lock Enable
Value Name Description 0 - the DMA never locks bus access. 1 - USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration. - BUFF_LENGTH: Buffer Byte Length (Write-only)
-
-
-
UDPHS UDPHS DMA Channel Status Register (channel = 2)
Name: UDPHS_DMASTATUS2
Access: read-write
Address: 0x400A432C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_COUNT | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_COUNT | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB |
- CHANN_ENB: Channel Enable Status
Value Name Description 0 - if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx register LDNXT_DSC bit is set. 1 - if set, the DMA channel is currently enabled and transfers data upon request. - CHANN_ACT: Channel Active Status
Value Name Description 0 - the DMA channel is no longer trying to source the packet data. 1 - the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel. - END_TR_ST: End of Channel Transfer Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer. - END_BF_ST: End of Channel Buffer Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when the BUFF_COUNT downcount reach zero. - DESC_LDST: Descriptor Loaded Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when a descriptor has been loaded from the system bus. - BUFF_COUNT: Buffer Byte Count
-
UDPHS UDPHS DMA Next Descriptor Address Register (channel = 3)
Name: UDPHS_DMANXTDSC3
Access: read-write
Address: 0x400A4330
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NXT_DSC_ADD | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NXT_DSC_ADD | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NXT_DSC_ADD | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NXT_DSC_ADD |
- NXT_DSC_ADD
-
UDPHS UDPHS DMA Channel Address Register (channel = 3)
Name: UDPHS_DMAADDRESS3
Access: read-write
Address: 0x400A4334
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_ADD | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_ADD | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BUFF_ADD | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUFF_ADD |
- BUFF_ADD
-
UDPHS UDPHS DMA Channel Control Register (channel = 3)
Name: UDPHS_DMACONTROL3
Access: read-write
Address: 0x400A4338
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_LENGTH | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_LENGTH | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB |
- CHANN_ENB
- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable (Command)
- END_TR_EN: End of Transfer Enable (Control)
Value Name Description 0 - USB end of transfer is ignored. 1 - UDPHS device can put an end to the current buffer transfer. - END_B_EN: End of Buffer Enable (Control)
Value Name Description 0 - DMA Buffer End has no impact on USB packet transfer. 1 - endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID and SHRT_PCKT fields) at DMA Buffer End, i.e. when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0. - END_TR_IT: End of Transfer Interrupt Enable
Value Name Description 0 - UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST rising. 1 - an interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer. - END_BUFFIT: End of Buffer Interrupt Enable
Value Name Description 0 - UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt. 1 - an interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero. - DESC_LD_IT: Descriptor Loaded Interrupt Enable
Value Name Description 0 - UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt. 1 - an interrupt is generated when a descriptor has been loaded from the bus. - BURST_LCK: Burst Lock Enable
Value Name Description 0 - the DMA never locks bus access. 1 - USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration. - BUFF_LENGTH: Buffer Byte Length (Write-only)
-
-
-
UDPHS UDPHS DMA Channel Status Register (channel = 3)
Name: UDPHS_DMASTATUS3
Access: read-write
Address: 0x400A433C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_COUNT | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_COUNT | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB |
- CHANN_ENB: Channel Enable Status
Value Name Description 0 - if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx register LDNXT_DSC bit is set. 1 - if set, the DMA channel is currently enabled and transfers data upon request. - CHANN_ACT: Channel Active Status
Value Name Description 0 - the DMA channel is no longer trying to source the packet data. 1 - the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel. - END_TR_ST: End of Channel Transfer Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer. - END_BF_ST: End of Channel Buffer Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when the BUFF_COUNT downcount reach zero. - DESC_LDST: Descriptor Loaded Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when a descriptor has been loaded from the system bus. - BUFF_COUNT: Buffer Byte Count
-
UDPHS UDPHS DMA Next Descriptor Address Register (channel = 4)
Name: UDPHS_DMANXTDSC4
Access: read-write
Address: 0x400A4340
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NXT_DSC_ADD | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NXT_DSC_ADD | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NXT_DSC_ADD | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NXT_DSC_ADD |
- NXT_DSC_ADD
-
UDPHS UDPHS DMA Channel Address Register (channel = 4)
Name: UDPHS_DMAADDRESS4
Access: read-write
Address: 0x400A4344
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_ADD | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_ADD | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BUFF_ADD | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUFF_ADD |
- BUFF_ADD
-
UDPHS UDPHS DMA Channel Control Register (channel = 4)
Name: UDPHS_DMACONTROL4
Access: read-write
Address: 0x400A4348
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_LENGTH | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_LENGTH | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB |
- CHANN_ENB
- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable (Command)
- END_TR_EN: End of Transfer Enable (Control)
Value Name Description 0 - USB end of transfer is ignored. 1 - UDPHS device can put an end to the current buffer transfer. - END_B_EN: End of Buffer Enable (Control)
Value Name Description 0 - DMA Buffer End has no impact on USB packet transfer. 1 - endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID and SHRT_PCKT fields) at DMA Buffer End, i.e. when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0. - END_TR_IT: End of Transfer Interrupt Enable
Value Name Description 0 - UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST rising. 1 - an interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer. - END_BUFFIT: End of Buffer Interrupt Enable
Value Name Description 0 - UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt. 1 - an interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero. - DESC_LD_IT: Descriptor Loaded Interrupt Enable
Value Name Description 0 - UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt. 1 - an interrupt is generated when a descriptor has been loaded from the bus. - BURST_LCK: Burst Lock Enable
Value Name Description 0 - the DMA never locks bus access. 1 - USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration. - BUFF_LENGTH: Buffer Byte Length (Write-only)
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UDPHS UDPHS DMA Channel Status Register (channel = 4)
Name: UDPHS_DMASTATUS4
Access: read-write
Address: 0x400A434C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_COUNT | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_COUNT | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB |
- CHANN_ENB: Channel Enable Status
Value Name Description 0 - if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx register LDNXT_DSC bit is set. 1 - if set, the DMA channel is currently enabled and transfers data upon request. - CHANN_ACT: Channel Active Status
Value Name Description 0 - the DMA channel is no longer trying to source the packet data. 1 - the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel. - END_TR_ST: End of Channel Transfer Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer. - END_BF_ST: End of Channel Buffer Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when the BUFF_COUNT downcount reach zero. - DESC_LDST: Descriptor Loaded Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when a descriptor has been loaded from the system bus. - BUFF_COUNT: Buffer Byte Count
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UDPHS UDPHS DMA Next Descriptor Address Register (channel = 5)
Name: UDPHS_DMANXTDSC5
Access: read-write
Address: 0x400A4350
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NXT_DSC_ADD | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NXT_DSC_ADD | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NXT_DSC_ADD | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NXT_DSC_ADD |
- NXT_DSC_ADD
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UDPHS UDPHS DMA Channel Address Register (channel = 5)
Name: UDPHS_DMAADDRESS5
Access: read-write
Address: 0x400A4354
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_ADD | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_ADD | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BUFF_ADD | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUFF_ADD |
- BUFF_ADD
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UDPHS UDPHS DMA Channel Control Register (channel = 5)
Name: UDPHS_DMACONTROL5
Access: read-write
Address: 0x400A4358
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_LENGTH | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_LENGTH | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB |
- CHANN_ENB
- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable (Command)
- END_TR_EN: End of Transfer Enable (Control)
Value Name Description 0 - USB end of transfer is ignored. 1 - UDPHS device can put an end to the current buffer transfer. - END_B_EN: End of Buffer Enable (Control)
Value Name Description 0 - DMA Buffer End has no impact on USB packet transfer. 1 - endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID and SHRT_PCKT fields) at DMA Buffer End, i.e. when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0. - END_TR_IT: End of Transfer Interrupt Enable
Value Name Description 0 - UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST rising. 1 - an interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer. - END_BUFFIT: End of Buffer Interrupt Enable
Value Name Description 0 - UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt. 1 - an interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero. - DESC_LD_IT: Descriptor Loaded Interrupt Enable
Value Name Description 0 - UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt. 1 - an interrupt is generated when a descriptor has been loaded from the bus. - BURST_LCK: Burst Lock Enable
Value Name Description 0 - the DMA never locks bus access. 1 - USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration. - BUFF_LENGTH: Buffer Byte Length (Write-only)
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UDPHS UDPHS DMA Channel Status Register (channel = 5)
Name: UDPHS_DMASTATUS5
Access: read-write
Address: 0x400A435C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUFF_COUNT | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUFF_COUNT | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB |
- CHANN_ENB: Channel Enable Status
Value Name Description 0 - if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx register LDNXT_DSC bit is set. 1 - if set, the DMA channel is currently enabled and transfers data upon request. - CHANN_ACT: Channel Active Status
Value Name Description 0 - the DMA channel is no longer trying to source the packet data. 1 - the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel. - END_TR_ST: End of Channel Transfer Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer. - END_BF_ST: End of Channel Buffer Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when the BUFF_COUNT downcount reach zero. - DESC_LDST: Descriptor Loaded Status
Value Name Description 0 - cleared automatically when read by software. 1 - set by hardware when a descriptor has been loaded from the system bus. - BUFF_COUNT: Buffer Byte Count
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